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* Added 0x0D to 2-byte opcode extension table for prefetch* variantsKay Tiong Khoo2013-02-121-0/+1
| | | | | | | Fixed decode of existing 3dNow prefetchw instruction Intel is scheduled to add a compatible prefetchw (same encoding) to future CPUs git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174920 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow targets to add custom asm operand matching logic.Jim Grosbach2013-02-061-0/+9
| | | | | | | | | | For example, ARM has several instructions with a literal '#0' immediate in the syntax that's not represented as an actual operand. The asm matcher is expected a token operand, but the parser will have created an immediate operand. This is currently handled by dedicated per-instruction C++ munging of the ParsedAsmOperand list, but will be better handled by this hook. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174487 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix commentsEli Bendersky2013-02-051-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174390 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch that sets the EmitAlias flag in td files Jack Carter2013-02-051-1/+4
| | | | | | | | | | | | | | | and enables the instruction printer to print aliased instructions. Due to usage of RegisterOperands a change in common code (utils/TableGen/AsmWriterEmitter.cpp) is required to get the correct register value if it is a RegisterOperand. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174358 91177308-0d34-0410-b5e6-96231b3b80d8
* MachineModel: Inconsequential TableGen SubtargetEmitter fix.Andrew Trick2013-02-011-1/+15
| | | | | | | | Drive by fix. I noticed some missing logic that might bite future users. This shouldn't affect the final output on currently modeled targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174142 91177308-0d34-0410-b5e6-96231b3b80d8
* Clarify intent.Jakob Stoklund Olesen2013-01-311-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174068 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AArch64 as an experimental target.Tim Northover2013-01-311-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for AArch64 (ARM's 64-bit architecture) to LLVM in the "experimental" category. Currently, it won't be built unless requested explicitly. This initial commit should have support for: + Assembly of all scalar (i.e. non-NEON, non-Crypto) instructions (except the late addition CRC instructions). + CodeGen features required for C++03 and C99. + Compilation for the "small" memory model: code+static data < 4GB. + Absolute and position-independent code. + GNU-style (i.e. "__thread") TLS. + Debugging information. The principal omission, currently, is performance tuning. This patch excludes the NEON support also reviewed due to an outbreak of batshit insanity in our legal department. That will be committed soon bringing the changes to precisely what has been approved. Further reviews would be gratefully received. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174054 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the AttributeSet instead of AttributeWithIndex.Bill Wendling2013-01-271-7/+6
| | | | | | | | In the future, AttributeWithIndex won't be used anymore. Besides, it exposes the internals of the AttributeSet to outside users, which isn't goodness. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173606 91177308-0d34-0410-b5e6-96231b3b80d8
* [ms-inline asm] Address the FIXME in AsmParser.cpp.Chad Rosier2013-01-151-4/+8
| | | | | | | | | | // FIXME: Constraints are hard coded to 'm', but we need an 'r' // constraint for addressof. This needs to be cleaned up! Test cases are already in place. Specifically, clang/test/CodeGen/ms-inline-asm.c t15(), t16(), and t24(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172569 91177308-0d34-0410-b5e6-96231b3b80d8
* Support for half intrinsics. Pushes MMX into slower encoding path.Michael Ilseman2013-01-111-18/+20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172159 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen: Keep track of superclass reference ranges.Jordan Rose2013-01-101-2/+4
| | | | | | | | | | def foo : bar; ~~~ This allows us to produce more precise diagnostics about a certain superclass, and even provide fixits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172085 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove locale-dependence of enum mangling and use existing function.Tim Northover2013-01-101-14/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172077 91177308-0d34-0410-b5e6-96231b3b80d8
* Make TableGen mangle operand method names before putting in enum.Tim Northover2013-01-101-2/+13
| | | | | | | | | The purpose of this patch is to allow PredicateMethods to be set to something like "isUImm<8>", calling a C++ template method to reduce code duplication. For this to work, the PredicateMethod must be mangled into a valid C++ identifier for insertion into an enum. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172073 91177308-0d34-0410-b5e6-96231b3b80d8
* Check whether MCInst operand isImm before calling getImm.Tim Northover2013-01-091-4/+10
| | | | | | | | | When processing possible aliases, TableGen assumes that if an operand *can* be an immediate, then it always *will* be. This is incorrect for the AArch64 backend. This patch inserts a check in the generated code to make sure isImm is true first. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171972 91177308-0d34-0410-b5e6-96231b3b80d8
* MIsched: add an ILP window property to machine model.Andrew Trick2013-01-091-0/+1
| | | | | | | | | | This was an experimental option, but needs to be defined per-target. e.g. PPC A2 needs to aggressively hide latency. I converted some in-order scheduling tests to A2. Hal is working on more test cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171946 91177308-0d34-0410-b5e6-96231b3b80d8
* Sort a few more #include lines in tools/... unittests/... and utils/...Chandler Carruth2013-01-021-3/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171363 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen/FixedLenDecoderEmitter.cpp: Fix a potential mask overflow in ↵NAKAMURA Takumi2012-12-261-1/+1
| | | | | | | | fieldFromInstruction(). Reported by Yang Yongyong, thanks! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171101 91177308-0d34-0410-b5e6-96231b3b80d8
* Added 6 more value types: v32i1, v64i1, v32i16, v32i8, v64i8, v8f64Elena Demikhovsky2012-12-241-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171026 91177308-0d34-0410-b5e6-96231b3b80d8
* Change 'AttrVal' to 'AttrKind' to better reflect that it's a kind of ↵Bill Wendling2012-12-221-1/+1
| | | | | | attribute instead of the value of the attribute. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170972 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix an uninitialized member variable, found by -fsanitize=bool.Richard Smith2012-12-201-7/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170627 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Add MCInstrDesc::mayAffectControlFlow() method.Jim Grosbach2012-12-191-5/+5
| | | | | | | | | MC disassembler clients (LLDB) are interested in querying if an instruction may affect control flow other than by virtue of being an explicit branch instruction. For example, instructions which write directly to the PC on some architectures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170610 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove edis - the enhanced disassembler. Fixes PR14654.Roman Divacky2012-12-194-1020/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170578 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename the 'Attributes' class to 'Attribute'. It's going to represent a ↵Bill Wendling2012-12-191-6/+6
| | | | | | single attribute in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170502 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR14568: Avoid the DFA packetizer from making an invalid readAnshuman Dasgupta2012-12-101-1/+10
| | | | | | | | | | | beyond array bounds. No test case since I cannot reproduce an ICE with this bug. According to Carlos -- the bug reporter -- a segfault occurs only when LLVM is compiled with a specific version of GCC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169783 91177308-0d34-0410-b5e6-96231b3b80d8
* s/AttrListPtr/AttributeSet/g to better label what this class is going to be ↵Bill Wendling2012-12-071-5/+5
| | | | | | in the near future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169651 91177308-0d34-0410-b5e6-96231b3b80d8
* RegisterPresssureTracker: Track live physical register by unit.Andrew Trick2012-12-051-2/+6
| | | | | | | | This is much simpler to reason about, more efficient, and fixes some corner cases involving implicit super-register defs. Fixed rdar://12797931. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169425 91177308-0d34-0410-b5e6-96231b3b80d8
* RegisterPressure API. Add support for physical register units.Andrew Trick2012-12-053-11/+115
| | | | | | | | | | | | | At build-time register pressure was always computed in terms of register units. But the compile-time API was expressed in terms of register classes because it was intended for virtual registers (and physical register units weren't yet used anywhere in codegen). Now that the codegen uses physreg units consistently, prepare for tracking register pressure also in terms of live units, not live registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169360 91177308-0d34-0410-b5e6-96231b3b80d8
* Copy clang/Driver/<Option parsing stuff> to llvm.Michael J. Spencer2012-12-054-1/+276
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169344 91177308-0d34-0410-b5e6-96231b3b80d8
* Sort the #include lines for utils/...Chandler Carruth2012-12-0430-63/+54
| | | | | | | I've tried to find main moudle headers where possible, but the TableGen stuff may warrant someone else looking at it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169251 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an MCPhysReg typedef to replace naked uint16_t.Jakob Stoklund Olesen2012-11-291-7/+7
| | | | | | Use this type for arrays of physical registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168850 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove all references to TargetInstrInfoImpl.Jakob Stoklund Olesen2012-11-281-2/+2
| | | | | | This class has been merged into its super-class TargetInstrInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168760 91177308-0d34-0410-b5e6-96231b3b80d8
* Make the AttrListPtr object a part of the LLVMContext.Bill Wendling2012-11-201-1/+1
| | | | | | | | | | When code deletes the context, the AttributeImpls that the AttrListPtr points to are now invalid. Therefore, instead of keeping a separate managed static for the AttrListPtrs that's reference counted, move it into the LLVMContext and delete it when deleting the AttributeImpls. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168354 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove hard coded registers in ARM ldrexd and strexd instructionsWeiming Zhao2012-11-161-0/+1
| | | | | | | | | | | This patch replaces the hard coded GPR pair [R0, R1] of Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with even/odd GPRPair reg class. Similar to the lowering of atomic_64 operation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168207 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix issue with invalid flat operand numberEvandro Menezes2012-11-091-3/+1
| | | | | | | | | | Avoid iterating over list of operands beyond the number of operands in it. PS: this fixes issue with revision #167634. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167635 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix issue with invalid flat operand numberEvandro Menezes2012-11-091-1/+6
| | | | | | | | | Avoid iterating over list of operands beyond the number of operands in it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167634 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support of RTM from TSX extensionMichael Liao2012-11-081-8/+9
| | | | | | | | | | - Add RTM code generation support throught 3 X86 intrinsics: xbegin()/xend() to start/end a transaction region, and xabort() to abort a tranaction region git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167573 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a build problem with xlc. The error message wasRafael Espindola2012-11-022-2/+2
| | | | | | | | | "../llvm-git/utils/TableGen/CodeGenSchedule.cpp", line 1594.12: 1540-0218 (S) The call does not match any parameter list for "operator+". "../llvm-git/include/llvm/ADT/STLExtras.h", line 130.1: 1540-1283 (I) "template <class _Iterator, class Func> llvm::operator+(mapped_iterator<_Iterator,Func>::difference_type, const mapped_iterator<_Iterator,Func> &)" is not a viable candidate. Patch by Kai. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167311 91177308-0d34-0410-b5e6-96231b3b80d8
* Generate a table-driven version of TRI::composeSubRegIndices().Jakob Stoklund Olesen2012-11-011-26/+102
| | | | | | | | | | Explicitly allow composition of null sub-register indices, and handle that common case in an inlinable stub. Use a compressed table implementation instead of the previous nested switches which generated pretty bad code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167190 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't return false when the function's return type is a pointer.Kaelyn Uhrain2012-10-251-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166719 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove exception handling usage from tblgen.Joerg Sonnenberger2012-10-2526-305/+375
| | | | | | | | | | | | Most places can use PrintFatalError as the unwinding mechanism was not used for anything other than printing the error. The single exception was CodeGenDAGPatterns.cpp, where intermediate errors during type resolution were ignored to simplify incremental platform development. This use is replaced by an error flag in TreePattern and bailout earlier in various places if it is set. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166712 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused member & unnecessary semicolon.David Blaikie2012-10-251-3/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166694 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/utils/TableGen/CMakeLists.txt: Update corresponding to r166685.NAKAMURA Takumi2012-10-251-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166686 91177308-0d34-0410-b5e6-96231b3b80d8
* add TableGen support to create relationship maps between instructionsSebastian Pop2012-10-253-0/+612
| | | | | | | | | | | Relationship maps are represented as InstrMapping records which are parsed by TableGen and the information is used to construct mapping tables to represent appropriate relations between instructions. These tables are emitted into XXXGenInstrInfo.inc file along with the functions to query them. Patch by Jyotsna Verma <jverma@codeaurora.org>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166685 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't use stack unwinding to provide the location information forJoerg Sonnenberger2012-10-244-69/+77
| | | | | | | SetTheory, but pass down the location explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166629 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow the commuted form of tied-operand constraints in tablegen ("$dst = $src",Lang Hames2012-10-201-5/+6
| | | | | | | rather than "$src = $dst"). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166382 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an enum for the return and function indexes into the AttrListPtr object. ↵Bill Wendling2012-10-151-2/+2
| | | | | | This gets rid of some magic numbers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165924 91177308-0d34-0410-b5e6-96231b3b80d8
* Attributes RewriteBill Wendling2012-10-151-4/+4
| | | | | | | | | | | Convert the internal representation of the Attributes class into a pointer to an opaque object that's uniqued by and stored in the LLVMContext object. The Attributes class then becomes a thin wrapper around this opaque object. Eventually, the internal representation will be expanded to include attributes that represent code generation options, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165917 91177308-0d34-0410-b5e6-96231b3b80d8
* [ms-inline asm] Use the new API introduced in r165830 in lieu of theChad Rosier2012-10-121-22/+15
| | | | | | | | MapAndConstraints vector. Also remove the unused Kind argument. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165833 91177308-0d34-0410-b5e6-96231b3b80d8
* Change (!list.size() == 0) to (!list.empty()). No functional change.Richard Trieu2012-10-121-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165812 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unnecessary classof()'sSean Silva2012-10-111-2/+0
| | | | | | | isa<> et al. automatically infer when the cast is an upcast (including a self-cast), so these are no longer necessary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165767 91177308-0d34-0410-b5e6-96231b3b80d8
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