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* Added TargetInstrDescriptor::numDefs - num of results.Evan Cheng2007-08-021-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40709 91177308-0d34-0410-b5e6-96231b3b80d8
* More explicit keywords.Dan Gohman2007-07-301-1/+1
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* VStudio compiler errors and placing Function*->ExFunc map under ↵Chuck Rose III2007-07-271-2/+2
| | | | | | | | | | | | | ManagedStatic control. This commit fixes two things. One is a pair of VStudio compiler errors stemming from variables which defined within the for loop statement and also within the body of the for loop. I fixed these by renaming one of the two variables. Additionally, I've made the Function*->ExFunc map in ExternalFunctions.cpp a ManagedStatic object, so that cleanup will be done on llvm_shutdown. In repeated uses of the interpreter, where the same Function* address may get used for completely differnet functions, this was causing a crash. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40558 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a pasto in a comment.Dan Gohman2007-07-261-1/+1
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* Have register info provide the inverse mapping of register->superregisters. ↵Christopher Lamb2007-07-261-3/+43
| | | | | | PR1350 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40519 91177308-0d34-0410-b5e6-96231b3b80d8
* Add target independent MachineInstr's to represent subreg insert/extract in ↵Christopher Lamb2007-07-264-6/+57
| | | | | | MBB's. PR1350 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40518 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach TableGen about the new vector types.Christopher Lamb2007-07-261-0/+4
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* A minor simplication in the generated code.Dan Gohman2007-07-241-2/+2
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* No need for noResults anymore.Evan Cheng2007-07-203-5/+2
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* Change instruction description to split OperandList into OutOperandList andEvan Cheng2007-07-194-4/+35
| | | | | | | | | | | | | | | | InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
* Work around a bogus gcc 4.2 warning.Chris Lattner2007-07-181-1/+2
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* Eliminate an unused parameter.Dan Gohman2007-07-132-3/+3
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* Try committing again. Add OptionalDefOperand. Remove clobbersPred.Evan Cheng2007-07-103-5/+11
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* ImmutablePredicateOperand is no more.Evan Cheng2007-07-062-4/+2
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* Add the byval attributeRafael Espindola2007-07-061-1/+2
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* Refactor code to add initial support for OptionalDefOperand.Evan Cheng2007-07-062-62/+72
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* Teach DAGISelEmitter about zero_reg.Evan Cheng2007-07-051-1/+8
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* Instructions with ImmutablePredicateOperand aren't really predicable since ↵Evan Cheng2007-07-052-2/+6
| | | | | | their predicates are fixed at isel time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37899 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert .cvsignore filesJohn Criswell2007-06-291-5/+0
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* One additional field in TargetRegisterDesc.Evan Cheng2007-06-271-1/+1
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* Add immediate sub-registers.Evan Cheng2007-06-261-0/+21
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* Revert the earlier change that removed the M_REMATERIALIZABLE machineDan Gohman2007-06-263-0/+3
| | | | | | | | | | instruction flag, and use the flag along with a virtual member function hook for targets to override if there are instructions that are only trivially rematerializable with specific operands (i.e. constant pool loads). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37728 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a typo in a comment.Dan Gohman2007-06-261-1/+1
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* silence warning when assertions are disabled.Chris Lattner2007-06-191-2/+1
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* Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoadDan Gohman2007-06-193-3/+0
| | | | | | | | | | | with a general target hook to identify rematerializable instructions. Some instructions are only rematerializable with specific operands, such as loads from constant pools, while others are always rematerializable. This hook allows both to be identified as being rematerializable with the same mechanism. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37644 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.Evan Cheng2007-06-193-0/+3
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* Add support to tablegen for specifying subregister classes on a per register ↵Christopher Lamb2007-06-133-0/+50
| | | | | | class basis. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37572 91177308-0d34-0410-b5e6-96231b3b80d8
* Add clobbersPred - instruction that clobbers condition code / register which ↵Evan Cheng2007-06-063-0/+3
| | | | | | are used to predicate instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37465 91177308-0d34-0410-b5e6-96231b3b80d8
* Patches by Chuck Rose to unbreak V Studio builds.Bill Wendling2007-06-041-0/+1
| | | | | | | Thanks Chuck! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37428 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the operator<< for MVT::ValueType in preparation for MVT::ValueTypeDan Gohman2007-06-043-7/+1
| | | | | | | | being changed from an enum to an integer type, which can't have a custom operator<< overload. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37412 91177308-0d34-0410-b5e6-96231b3b80d8
* The Intrinsic::getDeclaration function's Tys parameter only contains theReid Spencer2007-05-221-5/+12
| | | | | | | | | types of the iAny types involved in the overloaded intrinsic. Thus, we can't use the argument number as the index but have to count them separately in order to index Tys correctly. This patch rectifies this situation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37296 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename M_PREDICATED to M_PREDICABLE; opcode can be specified isPredicable ↵Evan Cheng2007-05-163-4/+4
| | | | | | without having a PredicateOperand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37116 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix CodeGen/PowerPC/2007-05-14-InlineAsmSelectCrash.ll, the other recentChris Lattner2007-05-151-5/+7
| | | | | | | patches are also needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37070 91177308-0d34-0410-b5e6-96231b3b80d8
* Added \!con(a,b) syntax to concatnate two dag fragments.Evan Cheng2007-05-157-179/+226
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* Mark all (not just the first) predicate operand M_PREDICATE_OPERAND.Evan Cheng2007-05-151-1/+1
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* PredicateOperand related bug fix.Evan Cheng2007-05-151-1/+3
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* If a PredicateOperand has an empty ExecuteAlways field, treat it as if a ↵Evan Cheng2007-05-081-4/+9
| | | | | | normal operand for isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36946 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an "implies" field to features. This indicates that, if the currentBill Wendling2007-05-041-46/+54
| | | | | | | | | feature is set, then the features in the implied list should be set also. The opposite is also enforced: if a feature in the implied list isn't set, then the feature that owns that implies list shouldn't be set either. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36756 91177308-0d34-0410-b5e6-96231b3b80d8
* A bit of feedback from Chris that I missed; error rather than asserting.Nate Begeman2007-05-011-2/+5
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* llvm bug #1350, parts 1, 2, and 3.Nate Begeman2007-05-011-0/+36
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* Update a comment to reflect recent changes in the type system.Dan Gohman2007-04-261-1/+1
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* bugfix: remember that ResNode was declared.Lauro Ramos Venancio2007-04-261-2/+3
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* Fix generation of certain scheduler itineraries.Christopher Lamb2007-04-221-1/+2
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* Bug fix; add super-registers sets.Evan Cheng2007-04-211-11/+58
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* Implement "general dynamic", "initial exec" and "local exec" TLS models forLauro Ramos Venancio2007-04-201-2/+5
| | | | | | | X86 32 bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36283 91177308-0d34-0410-b5e6-96231b3b80d8
* Add sub-registers sets.Evan Cheng2007-04-201-6/+61
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* For PR1328:Reid Spencer2007-04-161-2/+0
| | | | | | | | | Don't assert everytime an intrinsic name isn't recognized. Instead, make the assert optional when callin getIntrinsicID(). This allows the assembler to handle invalid intrinsic names gracefully. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36120 91177308-0d34-0410-b5e6-96231b3b80d8
* For PR1297:Reid Spencer2007-04-013-17/+35
| | | | | | | | | | | Implement code generation for overloaded intrinsic functions. The basic difference is that "actual" argument types must be provided when constructing intrinsic names and types. Also, for recognition, only the prefix is examined. If it matches, the suffix is assumed to match. The suffix is checked by the Verifier, however. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35539 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for the v1i64 type. This makes better code for this:Bill Wendling2007-03-261-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | #include <mmintrin.h> extern __m64 C; void baz(__v2si *A, __v2si *B) { *A = C; _mm_empty(); } We get this: _baz: call "L1$pb" "L1$pb": popl %eax movl L_C$non_lazy_ptr-"L1$pb"(%eax), %eax movq (%eax), %mm0 movl 4(%esp), %eax movq %mm0, (%eax) emms ret GCC gives us this: _baz: pushl %ebx call L3 "L00000000001$pb": L3: popl %ebx subl $8, %esp movl L_C$non_lazy_ptr-"L00000000001$pb"(%ebx), %eax movl (%eax), %edx movl 4(%eax), %ecx movl 16(%esp), %eax movl %edx, (%eax) movl %ecx, 4(%eax) emms addl $8, %esp popl %ebx ret git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35351 91177308-0d34-0410-b5e6-96231b3b80d8
* Recognize target instruction flag 'isReMaterializable'.Evan Cheng2007-03-193-0/+3
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