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* Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMR...Craig Topper2011-10-161-4/+0
* Make SMDiagnostic a little more sane. Instead of passing around note/warning...Chris Lattner2011-10-161-36/+37
* Enhance llvm::SourceMgr to support diagnostic ranges, the same way clang does...Chris Lattner2011-10-161-1/+1
* Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3...Craig Topper2011-10-162-6/+21
* Add a helper script to create branches and tag release candidates.Bill Wendling2011-10-161-0/+95
* Add a script that helps merge changes into a release branch.Bill Wendling2011-10-161-0/+72
* Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work ...Craig Topper2011-10-151-8/+50
* Fix threads/jobs CalculationDavid Greene2011-10-141-3/+4
* Add Helpful MessagesDavid Greene2011-10-141-0/+3
* Add Option to Skip InstallDavid Greene2011-10-141-4/+7
* Add Option to Skip gcc BuildDavid Greene2011-10-141-0/+8
* Add X86 ANDN instruction. Including instruction selection.Craig Topper2011-10-141-0/+2
* Ban rematerializable instructions with side effects.Jakob Stoklund Olesen2011-10-141-0/+6
* ARM parsing and encoding for the <option> form of LDC/STC instructions.Jim Grosbach2011-10-121-0/+1
* Remove extra semicolon.Eli Friedman2011-10-111-1/+1
* Fix disassembling of popcntw. Also remove some code that says it accounts for...Craig Topper2011-10-112-2/+15
* Emit full ED initializers even for pseudo-instructions.Jakob Stoklund Olesen2011-10-101-14/+14
* Insert dummy ED table entries for pseudo-instructions.Jakob Stoklund Olesen2011-10-101-3/+3
* ARM NEON assembly parsing and encoding for VDUP(scalar).Jim Grosbach2011-10-071-0/+3
* Remove MultidefsDavid Greene2011-10-072-2/+2
* Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 6...Craig Topper2011-10-071-0/+1
* Remove the Clang tblgen backends from LLVM.Peter Collingbourne2011-10-0614-4019/+0
* Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This w...Craig Topper2011-10-062-0/+9
* Build system infrastructure for multiple tblgens.Peter Collingbourne2011-10-062-16/+2
* Remove the TRI::getSubRegisterRegClass() hook.Jakob Stoklund Olesen2011-10-061-27/+2
* Vim Support for MultidefsDavid Greene2011-10-051-1/+1
* Emacs Support for MultidefsDavid Greene2011-10-051-1/+1
* Add TRI::getSubClassWithSubReg(RC, Idx) function.Jakob Stoklund Olesen2011-10-053-6/+67
* Properly use const_iterator.Jakob Stoklund Olesen2011-10-041-4/+4
* Teach TableGen to infer missing register classes.Jakob Stoklund Olesen2011-10-042-17/+194
* TableGen: Store all allocation orders together.Jakob Stoklund Olesen2011-10-042-14/+15
* TableGen: Privatize CodeGenRegisterClass::TheDef and Name.Jakob Stoklund Olesen2011-10-045-29/+32
* TableGen: Don't add synthetic Records to the RecordKeeper.Jakob Stoklund Olesen2011-10-041-1/+0
* Add support in the disassembler for ignoring the L-bit on certain VEX instruc...Craig Topper2011-10-044-20/+25
* Remove last references to hotpatch.Rafael Espindola2011-10-041-1/+1
* Find the strip tool that works with the specified SDKROOT. rdar://10165908Bob Wilson2011-10-031-4/+10
* Fix typo in r140954.Craig Topper2011-10-021-1/+0
* Fix disassembling of INVEPT and INVVPID to take operandsCraig Topper2011-10-011-0/+2
* Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2...Craig Topper2011-10-012-6/+18
* Move TableGen's parser and entry point into a libraryPeter Collingbourne2011-10-0169-6879/+129
* Subtarget getFeatureBits() returns a uint64_t, not unsigned.Bob Wilson2011-10-011-1/+1
* Use precomputed BitVector for CodeGenRegisterClass::hasSubClass().Jakob Stoklund Olesen2011-09-302-8/+15
* Store sub-class lists as a bit vector.Jakob Stoklund Olesen2011-09-301-21/+4
* Extract a slightly more general BitVector printer.Jakob Stoklund Olesen2011-09-301-7/+16
* Compute lists of super-classes in CodeGenRegisterClass.Jakob Stoklund Olesen2011-09-303-39/+43
* Implement VarListElementInit:: resolveListElementReferenceDavid Greene2011-09-301-2/+10
* Precompute a bit vector of register sub-classes.Jakob Stoklund Olesen2011-09-302-0/+35
* Order register classes topologically.Jakob Stoklund Olesen2011-09-302-1/+41
* Switch to ArrayRef<CodeGenRegisterClass*>.Jakob Stoklund Olesen2011-09-298-66/+58
* tblgen/ClangDiagnostics: Add support for split default warning "no-werror" andDaniel Dunbar2011-09-291-1/+17
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