aboutsummaryrefslogtreecommitdiffstats
path: root/include/llvm/Target/TargetSchedInfo.h
blob: a6a03b52490c65bbece10ab3c03a6fffa3264d9c (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
//===- Target/TargetSchedInfo.h - Target Instruction Sched Info -*- C++ -*-===//
//
//                     The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file describes the target machine to the instruction scheduler.
//
// NOTE: This file is currently sparc V9 specific.
//
//===----------------------------------------------------------------------===//

#ifndef LLVM_TARGET_TARGETSCHEDINFO_H
#define LLVM_TARGET_TARGETSCHEDINFO_H

#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/ADT/hash_map"
#include <string>

namespace llvm {

typedef long long CycleCount_t;
static const CycleCount_t HUGE_LATENCY = ~((long long) 1 << (sizeof(CycleCount_t)-2));
static const CycleCount_t INVALID_LATENCY = -HUGE_LATENCY;

//---------------------------------------------------------------------------
// class MachineResource
// class CPUResource
//
// Purpose:
//   Representation of a single machine resource used in specifying
//   resource usages of machine instructions for scheduling.
//---------------------------------------------------------------------------


typedef unsigned resourceId_t;

struct CPUResource {
  const std::string rname;
  resourceId_t rid;
  int maxNumUsers;   // MAXINT if no restriction

  CPUResource(const std::string& resourceName, int maxUsers);
  static CPUResource* getCPUResource(resourceId_t id);
private:
  static resourceId_t nextId;
};


//---------------------------------------------------------------------------
// struct InstrClassRUsage
// struct InstrRUsageDelta
// struct InstrIssueDelta
// struct InstrRUsage
//
// Purpose:
//   The first three are structures used to specify machine resource
//   usages for each instruction in a machine description file:
//    InstrClassRUsage : resource usages common to all instrs. in a class
//    InstrRUsageDelta : add/delete resource usage for individual instrs.
//    InstrIssueDelta  : add/delete instr. issue info for individual instrs
//
//   The last one (InstrRUsage) is the internal representation of
//   instruction resource usage constructed from the above three.
//---------------------------------------------------------------------------

const int MAX_NUM_SLOTS  = 32;
const int MAX_NUM_CYCLES = 32;

struct InstrClassRUsage {
  InstrSchedClass schedClass;
  int             totCycles;

  // Issue restrictions common to instructions in this class
  unsigned      maxNumIssue;
  bool          isSingleIssue;
  bool          breaksGroup;
  CycleCount_t  numBubbles;

  // Feasible slots to use for instructions in this class.
  // The size of vector S[] is `numSlots'.
  unsigned      numSlots;
  unsigned      feasibleSlots[MAX_NUM_SLOTS];

  // Resource usages common to instructions in this class.
  // The size of vector V[] is `numRUEntries'.
  unsigned      numRUEntries;
  struct {
    resourceId_t resourceId;
    unsigned    startCycle;
    int         numCycles;
  } V[MAX_NUM_CYCLES];
};

struct InstrRUsageDelta {
  MachineOpCode opCode;
  resourceId_t  resourceId;
  unsigned      startCycle;
  int  numCycles;
};

// Specify instruction issue restrictions for individual instructions
// that differ from the common rules for the class.
//
struct InstrIssueDelta {
  MachineOpCode opCode;
  bool isSingleIssue;
  bool breaksGroup;
  CycleCount_t numBubbles;
};


struct InstrRUsage {
  bool  sameAsClass;

  // Issue restrictions for this instruction
  bool  isSingleIssue;
  bool  breaksGroup;
  CycleCount_t numBubbles;

  // Feasible slots to use for this instruction.
  std::vector<bool> feasibleSlots;

  // Resource usages for this instruction, with one resource vector per cycle.
  CycleCount_t numCycles;
  std::vector<std::vector<resourceId_t> > resourcesByCycle;

private:
  // Conveniences for initializing this structure
  void setTo(const InstrClassRUsage& classRU);

  void addIssueDelta(const InstrIssueDelta& delta) {
    sameAsClass = false;
    isSingleIssue = delta.isSingleIssue;
    breaksGroup = delta.breaksGroup;
    numBubbles = delta.numBubbles;
  }

  void addUsageDelta(const InstrRUsageDelta& delta);
  void setMaxSlots(int maxNumSlots) {
    feasibleSlots.resize(maxNumSlots);
  }

  friend class TargetSchedInfo; // give access to these functions
};


//---------------------------------------------------------------------------
/// TargetSchedInfo - Common interface to machine information for
/// instruction scheduling
///
class TargetSchedInfo {
public:
  const TargetMachine& target;

  unsigned maxNumIssueTotal;
  int longestIssueConflict;

protected:
  inline const InstrRUsage& getInstrRUsage(MachineOpCode opCode) const {
    assert(opCode >= 0 && opCode < (int) instrRUsages.size());
    return instrRUsages[opCode];
  }
  const InstrClassRUsage& getClassRUsage(const InstrSchedClass& sc) const {
    assert(sc < numSchedClasses);
    return classRUsages[sc];
  }

private:
  TargetSchedInfo(const TargetSchedInfo &);  // DO NOT IMPLEMENT
  void operator=(const TargetSchedInfo &);  // DO NOT IMPLEMENT
public:
  TargetSchedInfo(const TargetMachine& tgt,
                  int _numSchedClasses,
                  const InstrClassRUsage* _classRUsages,
                  const InstrRUsageDelta* _usageDeltas,
                  const InstrIssueDelta*  _issueDeltas,
                  unsigned _numUsageDeltas,
                  unsigned _numIssueDeltas);
  virtual ~TargetSchedInfo() {}

  inline const TargetInstrInfo& getInstrInfo() const {
    return *mii;
  }

  inline int getNumSchedClasses()  const {
    return numSchedClasses;
  }

  inline  unsigned getMaxNumIssueTotal() const {
    return maxNumIssueTotal;
  }

  inline  unsigned getMaxIssueForClass(const InstrSchedClass& sc) const {
    assert(sc < numSchedClasses);
    return classRUsages[sc].maxNumIssue;
  }

  inline InstrSchedClass getSchedClass(MachineOpCode opCode) const {
    return getInstrInfo().getSchedClass(opCode);
  }

  inline  bool instrCanUseSlot(MachineOpCode opCode,
                               unsigned s) const {
    assert(s < getInstrRUsage(opCode).feasibleSlots.size() && "Invalid slot!");
    return getInstrRUsage(opCode).feasibleSlots[s];
  }

  inline int getLongestIssueConflict() const {
    return longestIssueConflict;
  }

  inline  int getMinIssueGap(MachineOpCode fromOp,
                             MachineOpCode toOp)   const {
    assert(fromOp < (int) issueGaps.size());
    const std::vector<int>& toGaps = issueGaps[fromOp];
    return (toOp < (int) toGaps.size())? toGaps[toOp] : 0;
  }

  inline const std::vector<MachineOpCode>&
    getConflictList(MachineOpCode opCode) const {
    assert(opCode < (int) conflictLists.size());
    return conflictLists[opCode];
  }

  inline  bool isSingleIssue(MachineOpCode opCode) const {
    return getInstrRUsage(opCode).isSingleIssue;
  }

  inline  bool breaksIssueGroup(MachineOpCode opCode) const {
    return getInstrRUsage(opCode).breaksGroup;
  }

  inline  unsigned numBubblesAfter(MachineOpCode opCode) const {
    return getInstrRUsage(opCode).numBubbles;
  }

  inline unsigned getCPUResourceNum(int rd)const{
    for(unsigned i=0;i<resourceNumVector.size();i++){
      if(resourceNumVector[i].first == rd) return resourceNumVector[i].second;
    }
    assert( 0&&"resource not found");
    return 0;
  }


protected:
  virtual void initializeResources();

private:
  void computeInstrResources(const std::vector<InstrRUsage>& instrRUForClasses);
  void computeIssueGaps(const std::vector<InstrRUsage>& instrRUForClasses);

  void setGap(int gap, MachineOpCode fromOp, MachineOpCode toOp) {
    std::vector<int>& toGaps = issueGaps[fromOp];
    if (toOp >= (int) toGaps.size())
      toGaps.resize(toOp+1);
    toGaps[toOp] = gap;
  }

public:
  std::vector<std::pair<int,int> > resourceNumVector;

protected:
  unsigned           numSchedClasses;
  const TargetInstrInfo*   mii;
  const InstrClassRUsage*  classRUsages;        // raw array by sclass
  const InstrRUsageDelta*  usageDeltas;         // raw array [1:numUsageDeltas]
  const InstrIssueDelta*   issueDeltas;         // raw array [1:numIssueDeltas]
  unsigned      numUsageDeltas;
  unsigned      numIssueDeltas;

  std::vector<InstrRUsage> instrRUsages;    // indexed by opcode
  std::vector<std::vector<int> > issueGaps; // indexed by [opcode1][opcode2]
  std::vector<std::vector<MachineOpCode> >
      conflictLists;   // indexed by [opcode]


  friend class ModuloSchedulingPass;
  friend class MSSchedule;

};

} // End llvm namespace

#endif