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//===-- MSP430ISelDAGToDAG.cpp - A dag to dag inst selector for MSP430 ----===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file defines an instruction selector for the MSP430 target.
//
//===----------------------------------------------------------------------===//
#include "MSP430.h"
#include "MSP430ISelLowering.h"
#include "MSP430TargetMachine.h"
#include "llvm/DerivedTypes.h"
#include "llvm/Function.h"
#include "llvm/Intrinsics.h"
#include "llvm/CallingConv.h"
#include "llvm/Constants.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include <queue>
#include <set>
using namespace llvm;
/// MSP430DAGToDAGISel - MSP430 specific code to select MSP430 machine
/// instructions for SelectionDAG operations.
///
namespace {
class MSP430DAGToDAGISel : public SelectionDAGISel {
MSP430TargetLowering &Lowering;
const MSP430Subtarget &Subtarget;
public:
MSP430DAGToDAGISel(MSP430TargetMachine &TM)
: SelectionDAGISel(TM),
Lowering(*TM.getTargetLowering()),
Subtarget(*TM.getSubtargetImpl()) { }
virtual void InstructionSelect();
virtual const char *getPassName() const {
return "MSP430 DAG->DAG Pattern Instruction Selection";
}
// Include the pieces autogenerated from the target description.
#include "MSP430GenDAGISel.inc"
private:
SDNode *Select(SDValue Op);
bool SelectAddr(SDValue Op, SDValue Addr, SDValue &Disp, SDValue &Base);
#ifndef NDEBUG
unsigned Indent;
#endif
};
} // end anonymous namespace
/// createMSP430ISelDag - This pass converts a legalized DAG into a
/// MSP430-specific DAG, ready for instruction scheduling.
///
FunctionPass *llvm::createMSP430ISelDag(MSP430TargetMachine &TM) {
return new MSP430DAGToDAGISel(TM);
}
bool MSP430DAGToDAGISel::SelectAddr(SDValue Op, SDValue Addr,
SDValue &Disp, SDValue &Base) {
// We don't support frame index stuff yet.
if (isa<FrameIndexSDNode>(Addr))
return false;
// Operand is a result from ADD with constant operand which fits into i16.
switch (Addr.getOpcode()) {
case ISD::ADD:
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
uint64_t CVal = CN->getZExtValue();
// Offset should fit into 16 bits.
if (((CVal << 48) >> 48) == CVal) {
// We don't support frame index stuff yet.
if (isa<FrameIndexSDNode>(Addr.getOperand(0)))
return false;
Base = Addr.getOperand(0);
Disp = CurDAG->getTargetConstant(CVal, MVT::i16);
return true;
}
}
break;
case MSP430ISD::Wrapper:
SDValue N0 = Addr.getOperand(0);
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
// We can match addresses of globals without any offsets
if (!G->getOffset()) {
Base = CurDAG->getTargetGlobalAddress(G->getGlobal(),
MVT::i16, 0);
Disp = CurDAG->getTargetConstant(0, MVT::i16);
return true;
}
}
break;
};
Base = Addr;
Disp = CurDAG->getTargetConstant(0, MVT::i16);
return true;
}
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
void MSP430DAGToDAGISel::InstructionSelect() {
DEBUG(BB->dump());
// Select target instructions for the DAG.
SelectRoot(*CurDAG);
CurDAG->RemoveDeadNodes();
}
SDNode *MSP430DAGToDAGISel::Select(SDValue Op) {
SDNode *Node = Op.getNode();
// Dump information about the Node being selected
#ifndef NDEBUG
DOUT << std::string(Indent, ' ') << "Selecting: ";
DEBUG(Node->dump(CurDAG));
DOUT << "\n";
Indent += 2;
#endif
// If we have a custom node, we already have selected!
if (Node->isMachineOpcode()) {
#ifndef NDEBUG
DOUT << std::string(Indent-2, ' ') << "== ";
DEBUG(Node->dump(CurDAG));
DOUT << "\n";
Indent -= 2;
#endif
return NULL;
}
// Instruction Selection not handled by the auto-generated tablegen selection
// should be handled here.
// Something like this:
// unsigned Opcode = Node->getOpcode();
// switch (Opcode) {
// default: break;
// case ISD::Foo:
// return SelectFoo(Node)
// }
// Select the default instruction
SDNode *ResNode = SelectCode(Op);
#ifndef NDEBUG
DOUT << std::string(Indent-2, ' ') << "=> ";
if (ResNode == NULL || ResNode == Op.getNode())
DEBUG(Op.getNode()->dump(CurDAG));
else
DEBUG(ResNode->dump(CurDAG));
DOUT << "\n";
Indent -= 2;
#endif
return ResNode;
}
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