aboutsummaryrefslogtreecommitdiffstats
path: root/lib/Target/NVPTX/NVPTXInstrInfo.cpp
blob: dabc3be43a3af9fdd0d9523ecd2448fa424532e9 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
//===- NVPTXInstrInfo.cpp - NVPTX Instruction Information -----------------===//
//
//                     The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the NVPTX implementation of the TargetInstrInfo class.
//
//===----------------------------------------------------------------------===//

#include "NVPTX.h"
#include "NVPTXInstrInfo.h"
#include "NVPTXTargetMachine.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/IR/Function.h"

using namespace llvm;

#define GET_INSTRINFO_CTOR_DTOR
#include "NVPTXGenInstrInfo.inc"

// Pin the vtable to this file.
void NVPTXInstrInfo::anchor() {}

NVPTXInstrInfo::NVPTXInstrInfo() : NVPTXGenInstrInfo(), RegInfo() {}

void NVPTXInstrInfo::copyPhysReg(
    MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL,
    unsigned DestReg, unsigned SrcReg, bool KillSrc) const {
  const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
  const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg);
  const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);

  if (DestRC != SrcRC)
    report_fatal_error("Attempted to created cross-class register copy");

  if (DestRC == &NVPTX::Int32RegsRegClass)
    BuildMI(MBB, I, DL, get(NVPTX::IMOV32rr), DestReg)
      .addReg(SrcReg, getKillRegState(KillSrc));
  else if (DestRC == &NVPTX::Int1RegsRegClass)
    BuildMI(MBB, I, DL, get(NVPTX::IMOV1rr), DestReg)
      .addReg(SrcReg, getKillRegState(KillSrc));
  else if (DestRC == &NVPTX::Float32RegsRegClass)
    BuildMI(MBB, I, DL, get(NVPTX::FMOV32rr), DestReg)
      .addReg(SrcReg, getKillRegState(KillSrc));
  else if (DestRC == &NVPTX::Int16RegsRegClass)
    BuildMI(MBB, I, DL, get(NVPTX::IMOV16rr), DestReg)
      .addReg(SrcReg, getKillRegState(KillSrc));
  else if (DestRC == &NVPTX::Int64RegsRegClass)
    BuildMI(MBB, I, DL, get(NVPTX::IMOV64rr), DestReg)
      .addReg(SrcReg, getKillRegState(KillSrc));
  else if (DestRC == &NVPTX::Float64RegsRegClass)
    BuildMI(MBB, I, DL, get(NVPTX::FMOV64rr), DestReg)
      .addReg(SrcReg, getKillRegState(KillSrc));
  else {
    llvm_unreachable("Bad register copy");
  }
}

bool NVPTXInstrInfo::isMoveInstr(const MachineInstr &MI, unsigned &SrcReg,
                                 unsigned &DestReg) const {
  // Look for the appropriate part of TSFlags
  bool isMove = false;

  unsigned TSFlags =
      (MI.getDesc().TSFlags & NVPTX::SimpleMoveMask) >> NVPTX::SimpleMoveShift;
  isMove = (TSFlags == 1);

  if (isMove) {
    MachineOperand dest = MI.getOperand(0);
    MachineOperand src = MI.getOperand(1);
    assert(dest.isReg() && "dest of a movrr is not a reg");
    assert(src.isReg() && "src of a movrr is not a reg");

    SrcReg = src.getReg();
    DestReg = dest.getReg();
    return true;
  }

  return false;
}

bool NVPTXInstrInfo::isReadSpecialReg(MachineInstr &MI) const {
  switch (MI.getOpcode()) {
  default:
    return false;
  case NVPTX::INT_PTX_SREG_NTID_X:
  case NVPTX::INT_PTX_SREG_NTID_Y:
  case NVPTX::INT_PTX_SREG_NTID_Z:
  case NVPTX::INT_PTX_SREG_TID_X:
  case NVPTX::INT_PTX_SREG_TID_Y:
  case NVPTX::INT_PTX_SREG_TID_Z:
  case NVPTX::INT_PTX_SREG_CTAID_X:
  case NVPTX::INT_PTX_SREG_CTAID_Y:
  case NVPTX::INT_PTX_SREG_CTAID_Z:
  case NVPTX::INT_PTX_SREG_NCTAID_X:
  case NVPTX::INT_PTX_SREG_NCTAID_Y:
  case NVPTX::INT_PTX_SREG_NCTAID_Z:
  case NVPTX::INT_PTX_SREG_WARPSIZE:
    return true;
  }
}

bool NVPTXInstrInfo::isLoadInstr(const MachineInstr &MI,
                                 unsigned &AddrSpace) const {
  bool isLoad = false;
  unsigned TSFlags =
      (MI.getDesc().TSFlags & NVPTX::isLoadMask) >> NVPTX::isLoadShift;
  isLoad = (TSFlags == 1);
  if (isLoad)
    AddrSpace = getLdStCodeAddrSpace(MI);
  return isLoad;
}

bool NVPTXInstrInfo::isStoreInstr(const MachineInstr &MI,
                                  unsigned &AddrSpace) const {
  bool isStore = false;
  unsigned TSFlags =
      (MI.getDesc().TSFlags & NVPTX::isStoreMask) >> NVPTX::isStoreShift;
  isStore = (TSFlags == 1);
  if (isStore)
    AddrSpace = getLdStCodeAddrSpace(MI);
  return isStore;
}

bool NVPTXInstrInfo::CanTailMerge(const MachineInstr *MI) const {
  unsigned addrspace = 0;
  if (MI->getOpcode() == NVPTX::INT_CUDA_SYNCTHREADS)
    return false;
  if (isLoadInstr(*MI, addrspace))
    if (addrspace == NVPTX::PTXLdStInstCode::SHARED)
      return false;
  if (isStoreInstr(*MI, addrspace))
    if (addrspace == NVPTX::PTXLdStInstCode::SHARED)
      return false;
  return true;
}

/// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
/// true if it cannot be understood (e.g. it's a switch dispatch or isn't
/// implemented for a target).  Upon success, this returns false and returns
/// with the following information in various cases:
///
/// 1. If this block ends with no branches (it just falls through to its succ)
///    just return false, leaving TBB/FBB null.
/// 2. If this block ends with only an unconditional branch, it sets TBB to be
///    the destination block.
/// 3. If this block ends with an conditional branch and it falls through to
///    an successor block, it sets TBB to be the branch destination block and a
///    list of operands that evaluate the condition. These
///    operands can be passed to other TargetInstrInfo methods to create new
///    branches.
/// 4. If this block ends with an conditional branch and an unconditional
///    block, it returns the 'true' destination in TBB, the 'false' destination
///    in FBB, and a list of operands that evaluate the condition. These
///    operands can be passed to other TargetInstrInfo methods to create new
///    branches.
///
/// Note that RemoveBranch and InsertBranch must be implemented to support
/// cases where this method returns success.
///
bool NVPTXInstrInfo::AnalyzeBranch(
    MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
    SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const {
  // If the block has no terminators, it just falls into the block after it.
  MachineBasicBlock::iterator I = MBB.end();
  if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
    return false;

  // Get the last instruction in the block.
  MachineInstr *LastInst = I;

  // If there is only one terminator instruction, process it.
  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
    if (LastInst->getOpcode() == NVPTX::GOTO) {
      TBB = LastInst->getOperand(0).getMBB();
      return false;
    } else if (LastInst->getOpcode() == NVPTX::CBranch) {
      // Block ends with fall-through condbranch.
      TBB = LastInst->getOperand(1).getMBB();
      Cond.push_back(LastInst->getOperand(0));
      return false;
    }
    // Otherwise, don't know what this is.
    return true;
  }

  // Get the instruction before it if it's a terminator.
  MachineInstr *SecondLastInst = I;

  // If there are three terminators, we don't know what sort of block this is.
  if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
    return true;

  // If the block ends with NVPTX::GOTO and NVPTX:CBranch, handle it.
  if (SecondLastInst->getOpcode() == NVPTX::CBranch &&
      LastInst->getOpcode() == NVPTX::GOTO) {
    TBB = SecondLastInst->getOperand(1).getMBB();
    Cond.push_back(SecondLastInst->getOperand(0));
    FBB = LastInst->getOperand(0).getMBB();
    return false;
  }

  // If the block ends with two NVPTX:GOTOs, handle it.  The second one is not
  // executed, so remove it.
  if (SecondLastInst->getOpcode() == NVPTX::GOTO &&
      LastInst->getOpcode() == NVPTX::GOTO) {
    TBB = SecondLastInst->getOperand(0).getMBB();
    I = LastInst;
    if (AllowModify)
      I->eraseFromParent();
    return false;
  }

  // Otherwise, can't handle this.
  return true;
}

unsigned NVPTXInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
  MachineBasicBlock::iterator I = MBB.end();
  if (I == MBB.begin())
    return 0;
  --I;
  if (I->getOpcode() != NVPTX::GOTO && I->getOpcode() != NVPTX::CBranch)
    return 0;

  // Remove the branch.
  I->eraseFromParent();

  I = MBB.end();

  if (I == MBB.begin())
    return 1;
  --I;
  if (I->getOpcode() != NVPTX::CBranch)
    return 1;

  // Remove the branch.
  I->eraseFromParent();
  return 2;
}

unsigned NVPTXInstrInfo::InsertBranch(
    MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
    const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const {
  // Shouldn't be a fall through.
  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
  assert((Cond.size() == 1 || Cond.size() == 0) &&
         "NVPTX branch conditions have two components!");

  // One-way branch.
  if (!FBB) {
    if (Cond.empty()) // Unconditional branch
      BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(TBB);
    else // Conditional branch
      BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg())
          .addMBB(TBB);
    return 1;
  }

  // Two-way Conditional Branch.
  BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()).addMBB(TBB);
  BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(FBB);
  return 2;
}