1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
|
//===- PTXInstrInfo.td - PTX Instruction defs -----------------*- tblgen-*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file describes the PTX instructions in TableGen format.
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Instruction format superclass
//===----------------------------------------------------------------------===//
include "PTXInstrFormats.td"
//===----------------------------------------------------------------------===//
// Instruction Pattern Stuff
//===----------------------------------------------------------------------===//
def load_global : PatFrag<(ops node:$ptr), (load node:$ptr), [{
if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
return PT->getAddressSpace() <= 255;
return false;
}]>;
// Addressing modes.
def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [], []>;
def ADDRii : ComplexPattern<i32, 2, "SelectADDRii", [], []>;
// Address operands
def MEMri : Operand<i32> {
let PrintMethod = "printMemOperand";
let MIOperandInfo = (ops RRegs32, i32imm);
}
def MEMii : Operand<i32> {
let PrintMethod = "printMemOperand";
let MIOperandInfo = (ops i32imm, i32imm);
}
//===----------------------------------------------------------------------===//
// PTX Specific Node Definitions
//===----------------------------------------------------------------------===//
// PTX allow generic 3-reg shifts like shl r0, r1, r2
def PTXshl : SDNode<"ISD::SHL", SDTIntBinOp>;
def PTXsrl : SDNode<"ISD::SRL", SDTIntBinOp>;
def PTXsra : SDNode<"ISD::SRA", SDTIntBinOp>;
def PTXexit
: SDNode<"PTXISD::EXIT", SDTNone, [SDNPHasChain]>;
def PTXret
: SDNode<"PTXISD::RET", SDTNone, [SDNPHasChain]>;
//===----------------------------------------------------------------------===//
// Instruction Class Templates
//===----------------------------------------------------------------------===//
multiclass INT3<string opcstr, SDNode opnode> {
def rr : InstPTX<(outs RRegs32:$d),
(ins RRegs32:$a, RRegs32:$b),
!strconcat(opcstr, ".%type\t$d, $a, $b"),
[(set RRegs32:$d, (opnode RRegs32:$a, RRegs32:$b))]>;
def ri : InstPTX<(outs RRegs32:$d),
(ins RRegs32:$a, i32imm:$b),
!strconcat(opcstr, ".%type\t$d, $a, $b"),
[(set RRegs32:$d, (opnode RRegs32:$a, imm:$b))]>;
}
// no %type directive, non-communtable
multiclass INT3ntnc<string opcstr, SDNode opnode> {
def rr : InstPTX<(outs RRegs32:$d),
(ins RRegs32:$a, RRegs32:$b),
!strconcat(opcstr, "\t$d, $a, $b"),
[(set RRegs32:$d, (opnode RRegs32:$a, RRegs32:$b))]>;
def ri : InstPTX<(outs RRegs32:$d),
(ins RRegs32:$a, i32imm:$b),
!strconcat(opcstr, "\t$d, $a, $b"),
[(set RRegs32:$d, (opnode RRegs32:$a, imm:$b))]>;
def ir : InstPTX<(outs RRegs32:$d),
(ins i32imm:$a, RRegs32:$b),
!strconcat(opcstr, "\t$d, $a, $b"),
[(set RRegs32:$d, (opnode imm:$a, RRegs32:$b))]>;
}
multiclass PTX_LD<string opstr, RegisterClass RC, PatFrag pat_load> {
def ri : InstPTX<(outs RC:$d),
(ins MEMri:$a),
!strconcat(opstr, ".%type\t$d, [$a]"),
[(set RC:$d, (pat_load ADDRri:$a))]>;
def ii : InstPTX<(outs RC:$d),
(ins MEMii:$a),
!strconcat(opstr, ".%type\t$d, [$a]"),
[(set RC:$d, (pat_load ADDRii:$a))]>;
}
//===----------------------------------------------------------------------===//
// Instructions
//===----------------------------------------------------------------------===//
///===- Integer Arithmetic Instructions -----------------------------------===//
defm ADD : INT3<"add", add>;
defm SUB : INT3<"sub", sub>;
///===- Logic and Shift Instructions --------------------------------------===//
defm SHL : INT3ntnc<"shl.b32", PTXshl>;
defm SRL : INT3ntnc<"shr.u32", PTXsrl>;
defm SRA : INT3ntnc<"shr.s32", PTXsra>;
///===- Data Movement and Conversion Instructions -------------------------===//
let neverHasSideEffects = 1 in {
// rely on isMoveInstr to separate MOVpp, MOVrr, etc.
def MOVpp
: InstPTX<(outs Preds:$d), (ins Preds:$a), "mov.pred\t$d, $a", []>;
def MOVrr
: InstPTX<(outs RRegs32:$d), (ins RRegs32:$a), "mov.%type\t$d, $a", []>;
}
let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
def MOVpi
: InstPTX<(outs Preds:$d), (ins i1imm:$a), "mov.pred\t$d, $a",
[(set Preds:$d, imm:$a)]>;
def MOVri
: InstPTX<(outs RRegs32:$d), (ins i32imm:$a), "mov.s32\t$d, $a",
[(set RRegs32:$d, imm:$a)]>;
}
defm LDg : PTX_LD<"ld.global", RRegs32, load_global>;
///===- Control Flow Instructions -----------------------------------------===//
let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
def EXIT : InstPTX<(outs), (ins), "exit", [(PTXexit)]>;
def RET : InstPTX<(outs), (ins), "ret", [(PTXret)]>;
}
|
