aboutsummaryrefslogtreecommitdiffstats
path: root/lib/Target/R600/AMDGPU.td
blob: a7d48b38ad50d6266ce42a832676faff160d8fca (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
//===-- AMDIL.td - AMDIL Tablegen files --*- tablegen -*-------------------===//
//
//                     The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//==-----------------------------------------------------------------------===//

include "llvm/Target/Target.td"

//===----------------------------------------------------------------------===//
// Subtarget Features
//===----------------------------------------------------------------------===//

// Debugging Features

def FeatureDumpCode : SubtargetFeature <"DumpCode",
        "DumpCode",
        "true",
        "Dump MachineInstrs in the CodeEmitter">;

def FeatureIRStructurizer : SubtargetFeature <"disable-irstructurizer",
        "EnableIRStructurizer",
        "false",
        "Disable IR Structurizer">;

def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
        "EnablePromoteAlloca",
        "true",
        "Enable promote alloca pass">;

// Target features

def FeatureIfCvt : SubtargetFeature <"disable-ifcvt",
        "EnableIfCvt",
        "false",
        "Disable the if conversion pass">;

def FeatureFP64 : SubtargetFeature<"fp64",
        "FP64",
        "true",
        "Enable double precision operations">;

def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
        "FP64Denormals",
        "true",
        "Enable double precision denormal handling",
        [FeatureFP64]>;

def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
        "FastFMAF32",
        "true",
        "Assuming f32 fma is at least as fast as mul + add",
        []>;

// Some instructions do not support denormals despite this flag. Using
// fp32 denormals also causes instructions to run at the double
// precision rate for the device.
def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
        "FP32Denormals",
        "true",
        "Enable single precision denormal handling">;

def Feature64BitPtr : SubtargetFeature<"64BitPtr",
        "Is64bit",
        "true",
        "Specify if 64-bit addressing should be used">;

def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
        "R600ALUInst",
        "false",
        "Older version of ALU instructions encoding">;

def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
        "HasVertexCache",
        "true",
        "Specify use of dedicated vertex cache">;

def FeatureCaymanISA : SubtargetFeature<"caymanISA",
        "CaymanISA",
        "true",
        "Use Cayman ISA">;

def FeatureCFALUBug : SubtargetFeature<"cfalubug",
        "CFALUBug",
        "true",
        "GPU has CF_ALU bug">;

// XXX - This should probably be removed once enabled by default
def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
        "EnableLoadStoreOpt",
        "true",
        "Enable SI load/store optimizer pass">;

def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
        "FlatAddressSpace",
        "true",
        "Support flat address space">;

def FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling",
        "EnableVGPRSpilling",
        "true",
        "Enable spilling of VGPRs to scratch memory">;

class SubtargetFeatureFetchLimit <string Value> :
                          SubtargetFeature <"fetch"#Value,
        "TexVTXClauseSize",
        Value,
        "Limit the maximum number of fetches in a clause to "#Value>;

def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;

class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
        "wavefrontsize"#Value,
        "WavefrontSize",
        !cast<string>(Value),
        "The number of threads per wavefront">;

def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;

class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
        "localmemorysize"#Value,
        "LocalMemorySize",
        !cast<string>(Value),
        "The size of local memory in bytes">;

class SubtargetFeatureGeneration <string Value,
                                  list<SubtargetFeature> Implies> :
        SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
                          Value#" GPU generation", Implies>;

def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;

def FeatureR600 : SubtargetFeatureGeneration<"R600",
        [FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]>;

def FeatureR700 : SubtargetFeatureGeneration<"R700",
        [FeatureFetchLimit16, FeatureLocalMemorySize0]>;

def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
        [FeatureFetchLimit16, FeatureLocalMemorySize32768]>;

def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
        [FeatureFetchLimit16, FeatureWavefrontSize64,
         FeatureLocalMemorySize32768]
>;

def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
        [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize32768,
         FeatureWavefrontSize64]>;

def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
        [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
         FeatureWavefrontSize64, FeatureFlatAddressSpace]>;

def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
        [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
         FeatureWavefrontSize64, FeatureFlatAddressSpace]>;

//===----------------------------------------------------------------------===//

def AMDGPUInstrInfo : InstrInfo {
  let guessInstructionProperties = 1;
  let noNamedPositionallyEncodedOperands = 1;
}

def AMDGPUAsmParser : AsmParser {
  // Some of the R600 registers have the same name, so this crashes.
  // For example T0_XYZW and T0_XY both have the asm name T0.
  let ShouldEmitMatchRegisterName = 0;
}

def AMDGPU : Target {
  // Pull in Instruction Info:
  let InstructionSet = AMDGPUInstrInfo;
  let AssemblyParsers = [AMDGPUAsmParser];
}

// Dummy Instruction itineraries for pseudo instructions
def ALU_NULL : FuncUnit;
def NullALU : InstrItinClass;

//===----------------------------------------------------------------------===//
// Predicate helper class
//===----------------------------------------------------------------------===//

class PredicateControl {
  Predicate SubtargetPredicate;
  list<Predicate> OtherPredicates = [];
  list<Predicate> Predicates = !listconcat([SubtargetPredicate],
                                            OtherPredicates);
}

// Include AMDGPU TD files
include "R600Schedule.td"
include "SISchedule.td"
include "Processors.td"
include "AMDGPUInstrInfo.td"
include "AMDGPUIntrinsics.td"
include "AMDGPURegisterInfo.td"
include "AMDGPUInstructions.td"
include "AMDGPUCallingConv.td"