1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
|
//===-- R600ClauseMergePass - Merge consecutive CF_ALU -------------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
/// \file
/// R600EmitClauseMarker pass emits CFAlu instruction in a conservative maneer.
/// This pass is merging consecutive CFAlus where applicable.
/// It needs to be called after IfCvt for best results.
//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "r600mergeclause"
#include "AMDGPU.h"
#include "R600Defines.h"
#include "R600InstrInfo.h"
#include "R600MachineFunctionInfo.h"
#include "R600RegisterInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
namespace {
static bool isCFAlu(const MachineInstr *MI) {
switch (MI->getOpcode()) {
case AMDGPU::CF_ALU:
case AMDGPU::CF_ALU_PUSH_BEFORE:
return true;
default:
return false;
}
}
class R600ClauseMergePass : public MachineFunctionPass {
private:
static char ID;
const R600InstrInfo *TII;
unsigned getCFAluSize(const MachineInstr *MI) const;
bool isCFAluEnabled(const MachineInstr *MI) const;
/// IfCvt pass can generate "disabled" ALU clause marker that need to be
/// removed and their content affected to the previous alu clause.
/// This function parse instructions after CFAlu untill it find a disabled
/// CFAlu and merge the content, or an enabled CFAlu.
void cleanPotentialDisabledCFAlu(MachineInstr *CFAlu) const;
/// Check whether LatrCFAlu can be merged into RootCFAlu and do it if
/// it is the case.
bool mergeIfPossible(MachineInstr *RootCFAlu, const MachineInstr *LatrCFAlu)
const;
public:
R600ClauseMergePass(TargetMachine &tm) : MachineFunctionPass(ID) { }
virtual bool runOnMachineFunction(MachineFunction &MF);
const char *getPassName() const;
};
char R600ClauseMergePass::ID = 0;
unsigned R600ClauseMergePass::getCFAluSize(const MachineInstr *MI) const {
assert(isCFAlu(MI));
return MI->getOperand(
TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::COUNT)).getImm();
}
bool R600ClauseMergePass::isCFAluEnabled(const MachineInstr *MI) const {
assert(isCFAlu(MI));
return MI->getOperand(
TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::Enabled)).getImm();
}
void R600ClauseMergePass::cleanPotentialDisabledCFAlu(MachineInstr *CFAlu)
const {
int CntIdx = TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::COUNT);
MachineBasicBlock::iterator I = CFAlu, E = CFAlu->getParent()->end();
I++;
do {
while (I!= E && !isCFAlu(I))
I++;
if (I == E)
return;
MachineInstr *MI = I++;
if (isCFAluEnabled(MI))
break;
CFAlu->getOperand(CntIdx).setImm(getCFAluSize(CFAlu) + getCFAluSize(MI));
MI->eraseFromParent();
} while (I != E);
}
bool R600ClauseMergePass::mergeIfPossible(MachineInstr *RootCFAlu,
const MachineInstr *LatrCFAlu) const {
assert(isCFAlu(RootCFAlu) && isCFAlu(LatrCFAlu));
int CntIdx = TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::COUNT);
unsigned RootInstCount = getCFAluSize(RootCFAlu),
LaterInstCount = getCFAluSize(LatrCFAlu);
unsigned CumuledInsts = RootInstCount + LaterInstCount;
if (CumuledInsts >= TII->getMaxAlusPerClause()) {
DEBUG(dbgs() << "Excess inst counts\n");
return false;
}
if (RootCFAlu->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE)
return false;
// Is KCache Bank 0 compatible ?
int Mode0Idx =
TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_MODE0);
int KBank0Idx =
TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_BANK0);
int KBank0LineIdx =
TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_ADDR0);
if (LatrCFAlu->getOperand(Mode0Idx).getImm() &&
RootCFAlu->getOperand(Mode0Idx).getImm() &&
(LatrCFAlu->getOperand(KBank0Idx).getImm() !=
RootCFAlu->getOperand(KBank0Idx).getImm() ||
LatrCFAlu->getOperand(KBank0LineIdx).getImm() !=
RootCFAlu->getOperand(KBank0LineIdx).getImm())) {
DEBUG(dbgs() << "Wrong KC0\n");
return false;
}
// Is KCache Bank 1 compatible ?
int Mode1Idx =
TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_MODE1);
int KBank1Idx =
TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_BANK1);
int KBank1LineIdx =
TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_ADDR1);
if (LatrCFAlu->getOperand(Mode1Idx).getImm() &&
RootCFAlu->getOperand(Mode1Idx).getImm() &&
(LatrCFAlu->getOperand(KBank1Idx).getImm() !=
RootCFAlu->getOperand(KBank1Idx).getImm() ||
LatrCFAlu->getOperand(KBank1LineIdx).getImm() !=
RootCFAlu->getOperand(KBank1LineIdx).getImm())) {
DEBUG(dbgs() << "Wrong KC0\n");
return false;
}
if (LatrCFAlu->getOperand(Mode0Idx).getImm()) {
RootCFAlu->getOperand(Mode0Idx).setImm(
LatrCFAlu->getOperand(Mode0Idx).getImm());
RootCFAlu->getOperand(KBank0Idx).setImm(
LatrCFAlu->getOperand(KBank0Idx).getImm());
RootCFAlu->getOperand(KBank0LineIdx).setImm(
LatrCFAlu->getOperand(KBank0LineIdx).getImm());
}
if (LatrCFAlu->getOperand(Mode1Idx).getImm()) {
RootCFAlu->getOperand(Mode1Idx).setImm(
LatrCFAlu->getOperand(Mode1Idx).getImm());
RootCFAlu->getOperand(KBank1Idx).setImm(
LatrCFAlu->getOperand(KBank1Idx).getImm());
RootCFAlu->getOperand(KBank1LineIdx).setImm(
LatrCFAlu->getOperand(KBank1LineIdx).getImm());
}
RootCFAlu->getOperand(CntIdx).setImm(CumuledInsts);
RootCFAlu->setDesc(TII->get(LatrCFAlu->getOpcode()));
return true;
}
bool R600ClauseMergePass::runOnMachineFunction(MachineFunction &MF) {
TII = static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo());
for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
BB != BB_E; ++BB) {
MachineBasicBlock &MBB = *BB;
MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
MachineBasicBlock::iterator LatestCFAlu = E;
while (I != E) {
MachineInstr *MI = I++;
if ((!TII->canBeConsideredALU(MI) && !isCFAlu(MI)) ||
TII->mustBeLastInClause(MI->getOpcode()))
LatestCFAlu = E;
if (!isCFAlu(MI))
continue;
cleanPotentialDisabledCFAlu(MI);
if (LatestCFAlu != E && mergeIfPossible(LatestCFAlu, MI)) {
MI->eraseFromParent();
} else {
assert(MI->getOperand(8).getImm() && "CF ALU instruction disabled");
LatestCFAlu = MI;
}
}
}
return false;
}
const char *R600ClauseMergePass::getPassName() const {
return "R600 Merge Clause Markers Pass";
}
} // end anonymous namespace
llvm::FunctionPass *llvm::createR600ClauseMergePass(TargetMachine &TM) {
return new R600ClauseMergePass(TM);
}
|
