aboutsummaryrefslogtreecommitdiffstats
path: root/lib/Target/SystemZ/SystemZInstrInfo.h
blob: 30f4c7dde446a12b86df24000b454b4a3e6013dd (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
//===-- SystemZInstrInfo.h - SystemZ instruction information ----*- C++ -*-===//
//
//                     The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the SystemZ implementation of the TargetInstrInfo class.
//
//===----------------------------------------------------------------------===//

#ifndef LLVM_TARGET_SYSTEMZINSTRINFO_H
#define LLVM_TARGET_SYSTEMZINSTRINFO_H

#include "SystemZ.h"
#include "SystemZRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"

#define GET_INSTRINFO_HEADER
#include "SystemZGenInstrInfo.inc"

namespace llvm {

class SystemZTargetMachine;

namespace SystemZII {
  enum {
    // See comments in SystemZInstrFormats.td.
    SimpleBDXLoad          = (1 << 0),
    SimpleBDXStore         = (1 << 1),
    Has20BitOffset         = (1 << 2),
    HasIndex               = (1 << 3),
    Is128Bit               = (1 << 4),
    AccessSizeMask         = (31 << 5),
    AccessSizeShift        = 5,
    CCValuesMask           = (15 << 10),
    CCValuesShift          = 10,
    CompareZeroCCMaskMask  = (15 << 14),
    CompareZeroCCMaskShift = 14,
    CCMaskFirst            = (1 << 18),
    CCMaskLast             = (1 << 19),
    IsLogical              = (1 << 20)
  };
  static inline unsigned getAccessSize(unsigned int Flags) {
    return (Flags & AccessSizeMask) >> AccessSizeShift;
  }
  static inline unsigned getCCValues(unsigned int Flags) {
    return (Flags & CCValuesMask) >> CCValuesShift;
  }
  static inline unsigned getCompareZeroCCMask(unsigned int Flags) {
    return (Flags & CompareZeroCCMaskMask) >> CompareZeroCCMaskShift;
  }

  // SystemZ MachineOperand target flags.
  enum {
    // Masks out the bits for the access model.
    MO_SYMBOL_MODIFIER = (1 << 0),

    // @GOT (aka @GOTENT)
    MO_GOT = (1 << 0)
  };
  // Classifies a branch.
  enum BranchType {
    // An instruction that branches on the current value of CC.
    BranchNormal,

    // An instruction that peforms a 32-bit signed comparison and branches
    // on the result.
    BranchC,

    // An instruction that peforms a 32-bit unsigned comparison and branches
    // on the result.
    BranchCL,

    // An instruction that peforms a 64-bit signed comparison and branches
    // on the result.
    BranchCG,

    // An instruction that peforms a 64-bit unsigned comparison and branches
    // on the result.
    BranchCLG,

    // An instruction that decrements a 32-bit register and branches if
    // the result is nonzero.
    BranchCT,

    // An instruction that decrements a 64-bit register and branches if
    // the result is nonzero.
    BranchCTG
  };
  // Information about a branch instruction.
  struct Branch {
    // The type of the branch.
    BranchType Type;

    // CCMASK_<N> is set if CC might be equal to N.
    unsigned CCValid;

    // CCMASK_<N> is set if the branch should be taken when CC == N.
    unsigned CCMask;

    // The target of the branch.
    const MachineOperand *Target;

    Branch(BranchType type, unsigned ccValid, unsigned ccMask,
           const MachineOperand *target)
      : Type(type), CCValid(ccValid), CCMask(ccMask), Target(target) {}
  };
}

class SystemZInstrInfo : public SystemZGenInstrInfo {
  const SystemZRegisterInfo RI;
  SystemZTargetMachine &TM;

  void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
  void splitAdjDynAlloc(MachineBasicBlock::iterator MI) const;
  void expandRXYPseudo(MachineInstr *MI, unsigned LowOpcode,
                       unsigned HighOpcode) const;
  void expandZExtPseudo(MachineInstr *MI, unsigned LowOpcode,
                        unsigned Size) const;
  void emitGRX32Move(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
                     DebugLoc DL, unsigned DestReg, unsigned SrcReg,
                     unsigned LowLowOpcode, unsigned Size, bool KillSrc) const;
  
public:
  explicit SystemZInstrInfo(SystemZTargetMachine &TM);

  // Override TargetInstrInfo.
  virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
                                       int &FrameIndex) const LLVM_OVERRIDE;
  virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
                                      int &FrameIndex) const LLVM_OVERRIDE;
  virtual bool isStackSlotCopy(const MachineInstr *MI, int &DestFrameIndex,
                               int &SrcFrameIndex) const LLVM_OVERRIDE;
  virtual bool AnalyzeBranch(MachineBasicBlock &MBB,
                             MachineBasicBlock *&TBB,
                             MachineBasicBlock *&FBB,
                             SmallVectorImpl<MachineOperand> &Cond,
                             bool AllowModify) const LLVM_OVERRIDE;
  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const LLVM_OVERRIDE;
  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
                                MachineBasicBlock *FBB,
                                const SmallVectorImpl<MachineOperand> &Cond,
                                DebugLoc DL) const LLVM_OVERRIDE;
  bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
                      unsigned &SrcReg2, int &Mask, int &Value) const
    LLVM_OVERRIDE;
  bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
                            unsigned SrcReg2, int Mask, int Value,
                            const MachineRegisterInfo *MRI) const LLVM_OVERRIDE;
  virtual bool isPredicable(MachineInstr *MI) const LLVM_OVERRIDE;
  virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
                                   unsigned ExtraPredCycles,
                                   const BranchProbability &Probability) const
    LLVM_OVERRIDE;
  virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
                                   unsigned NumCyclesT,
                                   unsigned ExtraPredCyclesT,
                                   MachineBasicBlock &FMBB,
                                   unsigned NumCyclesF,
                                   unsigned ExtraPredCyclesF,
                                   const BranchProbability &Probability) const
    LLVM_OVERRIDE;
  virtual bool
    PredicateInstruction(MachineInstr *MI,
                         const SmallVectorImpl<MachineOperand> &Pred) const
    LLVM_OVERRIDE;
  virtual void copyPhysReg(MachineBasicBlock &MBB,
                           MachineBasicBlock::iterator MBBI, DebugLoc DL,
                           unsigned DestReg, unsigned SrcReg,
                           bool KillSrc) const LLVM_OVERRIDE;
  virtual void
    storeRegToStackSlot(MachineBasicBlock &MBB,
                        MachineBasicBlock::iterator MBBI,
                        unsigned SrcReg, bool isKill, int FrameIndex,
                        const TargetRegisterClass *RC,
                        const TargetRegisterInfo *TRI) const LLVM_OVERRIDE;
  virtual void
    loadRegFromStackSlot(MachineBasicBlock &MBB,
                         MachineBasicBlock::iterator MBBI,
                         unsigned DestReg, int FrameIdx,
                         const TargetRegisterClass *RC,
                         const TargetRegisterInfo *TRI) const LLVM_OVERRIDE;
  virtual MachineInstr *
    convertToThreeAddress(MachineFunction::iterator &MFI,
                          MachineBasicBlock::iterator &MBBI,
                          LiveVariables *LV) const;
  virtual MachineInstr *
    foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
                          const SmallVectorImpl<unsigned> &Ops,
                          int FrameIndex) const;
  virtual MachineInstr *
    foldMemoryOperandImpl(MachineFunction &MF, MachineInstr* MI,
                          const SmallVectorImpl<unsigned> &Ops,
                          MachineInstr* LoadMI) const;
  virtual bool
    expandPostRAPseudo(MachineBasicBlock::iterator MBBI) const LLVM_OVERRIDE;
  virtual bool
    ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
    LLVM_OVERRIDE;

  // Return the SystemZRegisterInfo, which this class owns.
  const SystemZRegisterInfo &getRegisterInfo() const { return RI; }

  // Return the size in bytes of MI.
  uint64_t getInstSizeInBytes(const MachineInstr *MI) const;

  // Return true if MI is a conditional or unconditional branch.
  // When returning true, set Cond to the mask of condition-code
  // values on which the instruction will branch, and set Target
  // to the operand that contains the branch target.  This target
  // can be a register or a basic block.
  SystemZII::Branch getBranchInfo(const MachineInstr *MI) const;

  // Get the load and store opcodes for a given register class.
  void getLoadStoreOpcodes(const TargetRegisterClass *RC,
                           unsigned &LoadOpcode, unsigned &StoreOpcode) const;

  // Opcode is the opcode of an instruction that has an address operand,
  // and the caller wants to perform that instruction's operation on an
  // address that has displacement Offset.  Return the opcode of a suitable
  // instruction (which might be Opcode itself) or 0 if no such instruction
  // exists.
  unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const;

  // If Opcode is a load instruction that has a LOAD AND TEST form,
  // return the opcode for the testing form, otherwise return 0.
  unsigned getLoadAndTest(unsigned Opcode) const;

  // Return true if ROTATE AND ... SELECTED BITS can be used to select bits
  // Mask of the R2 operand, given that only the low BitSize bits of Mask are
  // significant.  Set Start and End to the I3 and I4 operands if so.
  bool isRxSBGMask(uint64_t Mask, unsigned BitSize,
                   unsigned &Start, unsigned &End) const;

  // If Opcode is a COMPARE opcode for which an associated COMPARE AND
  // BRANCH exists, return the opcode for the latter, otherwise return 0.
  // MI, if nonnull, is the compare instruction.
  unsigned getCompareAndBranch(unsigned Opcode,
                               const MachineInstr *MI = 0) const;

  // Emit code before MBBI in MI to move immediate value Value into
  // physical register Reg.
  void loadImmediate(MachineBasicBlock &MBB,
                     MachineBasicBlock::iterator MBBI,
                     unsigned Reg, uint64_t Value) const;
};
} // end namespace llvm

#endif