test/CodeGen/AArch64/arm64-vcvtxd_f32_f64.ll


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; RUN: llc < %s -march=arm64 | FileCheck %s

define float @fcvtxn(double %a) {
; CHECK-LABEL: fcvtxn:
; CHECK: fcvtxn s0, d0
; CHECK-NEXT: ret
  %vcvtxd.i = tail call float @llvm.aarch64.sisd.fcvtxn(double %a) nounwind
  ret float %vcvtxd.i
}

declare float @llvm.aarch64.sisd.fcvtxn(double) nounwind readnone