aboutsummaryrefslogtreecommitdiffstats
path: root/test/CodeGen/AArch64/arm64-vector-imm.ll
blob: 9fb088b9a4975c029769d96b962eb56e7efb55e8 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s

define <8 x i8> @v_orrimm(<8 x i8>* %A) nounwind {
; CHECK-LABEL: v_orrimm:
; CHECK-NOT: mov
; CHECK-NOT: mvn
; CHECK: orr
	%tmp1 = load <8 x i8>* %A
	%tmp3 = or <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1>
	ret <8 x i8> %tmp3
}

define <16 x i8> @v_orrimmQ(<16 x i8>* %A) nounwind {
; CHECK: v_orrimmQ
; CHECK-NOT: mov
; CHECK-NOT: mvn
; CHECK: orr
	%tmp1 = load <16 x i8>* %A
	%tmp3 = or <16 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1>
	ret <16 x i8> %tmp3
}

define <8 x i8> @v_bicimm(<8 x i8>* %A) nounwind {
; CHECK-LABEL: v_bicimm:
; CHECK-NOT: mov
; CHECK-NOT: mvn
; CHECK: bic
	%tmp1 = load <8 x i8>* %A
	%tmp3 = and <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 >
	ret <8 x i8> %tmp3
}

define <16 x i8> @v_bicimmQ(<16 x i8>* %A) nounwind {
; CHECK-LABEL: v_bicimmQ:
; CHECK-NOT: mov
; CHECK-NOT: mvn
; CHECK: bic
	%tmp1 = load <16 x i8>* %A
	%tmp3 = and <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 >
	ret <16 x i8> %tmp3
}

define <2 x double> @foo(<2 x double> %bar) nounwind {
; CHECK: foo
; CHECK: fmov.2d	v1, #1.0000000
  %add = fadd <2 x double> %bar, <double 1.0, double 1.0>
  ret <2 x double> %add
}

define <4 x i32> @movi_4s_imm_t1() nounwind readnone ssp {
entry:
; CHECK-LABEL: movi_4s_imm_t1:
; CHECK: movi.4s v0, #0x4b
  ret <4 x i32> <i32 75, i32 75, i32 75, i32 75>
}

define <4 x i32> @movi_4s_imm_t2() nounwind readnone ssp {
entry:
; CHECK-LABEL: movi_4s_imm_t2:
; CHECK: movi.4s v0, #0x4b, lsl #8
  ret <4 x i32> <i32 19200, i32 19200, i32 19200, i32 19200>
}

define <4 x i32> @movi_4s_imm_t3() nounwind readnone ssp {
entry:
; CHECK-LABEL: movi_4s_imm_t3:
; CHECK: movi.4s v0, #0x4b, lsl #16
  ret <4 x i32> <i32 4915200, i32 4915200, i32 4915200, i32 4915200>
}

define <4 x i32> @movi_4s_imm_t4() nounwind readnone ssp {
entry:
; CHECK-LABEL: movi_4s_imm_t4:
; CHECK: movi.4s v0, #0x4b, lsl #24
  ret <4 x i32> <i32 1258291200, i32 1258291200, i32 1258291200, i32 1258291200>
}

define <8 x i16> @movi_8h_imm_t5() nounwind readnone ssp {
entry:
; CHECK-LABEL: movi_8h_imm_t5:
; CHECK: movi.8h v0, #0x4b
  ret <8 x i16> <i16 75, i16 75, i16 75, i16 75, i16 75, i16 75, i16 75, i16 75>
}

; rdar://11989841
define <8 x i16> @movi_8h_imm_t6() nounwind readnone ssp {
entry:
; CHECK-LABEL: movi_8h_imm_t6:
; CHECK: movi.8h v0, #0x4b, lsl #8
  ret <8 x i16> <i16 19200, i16 19200, i16 19200, i16 19200, i16 19200, i16 19200, i16 19200, i16 19200>
}

define <4 x i32> @movi_4s_imm_t7() nounwind readnone ssp {
entry:
; CHECK-LABEL: movi_4s_imm_t7:
; CHECK: movi.4s v0, #0x4b, msl #8
ret <4 x i32> <i32 19455, i32 19455, i32 19455, i32 19455>
}

define <4 x i32> @movi_4s_imm_t8() nounwind readnone ssp {
entry:
; CHECK-LABEL: movi_4s_imm_t8:
; CHECK: movi.4s v0, #0x4b, msl #16
ret <4 x i32> <i32 4980735, i32 4980735, i32 4980735, i32 4980735>
}

define <16 x i8> @movi_16b_imm_t9() nounwind readnone ssp {
entry:
; CHECK-LABEL: movi_16b_imm_t9:
; CHECK: movi.16b v0, #0x4b
ret <16 x i8> <i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75,
               i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75>
}

define <2 x i64> @movi_2d_imm_t10() nounwind readnone ssp {
entry:
; CHECK-LABEL: movi_2d_imm_t10:
; CHECK: movi.2d v0, #0xff00ff00ff00ff
ret <2 x i64> <i64 71777214294589695, i64 71777214294589695>
}

define <4 x i32> @movi_4s_imm_t11() nounwind readnone ssp {
entry:
; CHECK-LABEL: movi_4s_imm_t11:
; CHECK: fmov.4s v0, #-0.32812500
ret <4 x i32> <i32 3198681088, i32 3198681088, i32 3198681088, i32 3198681088>
}

define <2 x i64> @movi_2d_imm_t12() nounwind readnone ssp {
entry:
; CHECK-LABEL: movi_2d_imm_t12:
; CHECK: fmov.2d v0, #-0.17187500
ret <2 x i64> <i64 13818732506632945664, i64 13818732506632945664>
}