1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
|
; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
; Optimized bitwise operations.
define i32 @my_clrbit(i32 %x) nounwind {
entry:
; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #31)
%x.addr = alloca i32, align 4
store i32 %x, i32* %x.addr, align 4
%0 = load i32, i32* %x.addr, align 4
%and = and i32 %0, 2147483647
ret i32 %and
}
define i64 @my_clrbit2(i64 %x) nounwind {
entry:
; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #31)
%x.addr = alloca i64, align 8
store i64 %x, i64* %x.addr, align 8
%0 = load i64, i64* %x.addr, align 8
%and = and i64 %0, -2147483649
ret i64 %and
}
define i64 @my_clrbit3(i64 %x) nounwind {
entry:
; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #31)
%x.addr = alloca i64, align 8
store i64 %x, i64* %x.addr, align 8
%0 = load i64, i64* %x.addr, align 8
%and = and i64 %0, 9223372036854775807
ret i64 %and
}
define i32 @my_clrbit4(i32 %x) nounwind {
entry:
; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #13)
%x.addr = alloca i32, align 4
store i32 %x, i32* %x.addr, align 4
%0 = load i32, i32* %x.addr, align 4
%and = and i32 %0, -8193
ret i32 %and
}
define i64 @my_clrbit5(i64 %x) nounwind {
entry:
; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #13)
%x.addr = alloca i64, align 8
store i64 %x, i64* %x.addr, align 8
%0 = load i64, i64* %x.addr, align 8
%and = and i64 %0, -8193
ret i64 %and
}
define i64 @my_clrbit6(i64 %x) nounwind {
entry:
; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #27)
%x.addr = alloca i64, align 8
store i64 %x, i64* %x.addr, align 8
%0 = load i64, i64* %x.addr, align 8
%and = and i64 %0, -576460752303423489
ret i64 %and
}
define zeroext i16 @my_setbit(i16 zeroext %crc) nounwind {
entry:
; CHECK: memh(r{{[0-9]+}}+#0){{ *}}={{ *}}setbit(#15)
%crc.addr = alloca i16, align 2
store i16 %crc, i16* %crc.addr, align 2
%0 = load i16, i16* %crc.addr, align 2
%conv = zext i16 %0 to i32
%or = or i32 %conv, 32768
%conv1 = trunc i32 %or to i16
store i16 %conv1, i16* %crc.addr, align 2
%1 = load i16, i16* %crc.addr, align 2
ret i16 %1
}
define i32 @my_setbit2(i32 %x) nounwind {
entry:
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}setbit(r{{[0-9]+}}, #15)
%x.addr = alloca i32, align 4
store i32 %x, i32* %x.addr, align 4
%0 = load i32, i32* %x.addr, align 4
%or = or i32 %0, 32768
ret i32 %or
}
define i64 @my_setbit3(i64 %x) nounwind {
entry:
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}setbit(r{{[0-9]+}}, #15)
%x.addr = alloca i64, align 8
store i64 %x, i64* %x.addr, align 8
%0 = load i64, i64* %x.addr, align 8
%or = or i64 %0, 32768
ret i64 %or
}
define i32 @my_setbit4(i32 %x) nounwind {
entry:
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}setbit(r{{[0-9]+}}, #31)
%x.addr = alloca i32, align 4
store i32 %x, i32* %x.addr, align 4
%0 = load i32, i32* %x.addr, align 4
%or = or i32 %0, -2147483648
ret i32 %or
}
define i64 @my_setbit5(i64 %x) nounwind {
entry:
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}setbit(r{{[0-9]+}}, #13)
%x.addr = alloca i64, align 8
store i64 %x, i64* %x.addr, align 8
%0 = load i64, i64* %x.addr, align 8
%or = or i64 %0, 35184372088832
ret i64 %or
}
define zeroext i16 @my_togglebit(i16 zeroext %crc) nounwind {
entry:
; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #15)
%crc.addr = alloca i16, align 2
store i16 %crc, i16* %crc.addr, align 2
%0 = load i16, i16* %crc.addr, align 2
%conv = zext i16 %0 to i32
%xor = xor i32 %conv, 32768
%conv1 = trunc i32 %xor to i16
store i16 %conv1, i16* %crc.addr, align 2
%1 = load i16, i16* %crc.addr, align 2
ret i16 %1
}
define i32 @my_togglebit2(i32 %x) nounwind {
entry:
; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #15)
%x.addr = alloca i32, align 4
store i32 %x, i32* %x.addr, align 4
%0 = load i32, i32* %x.addr, align 4
%xor = xor i32 %0, 32768
ret i32 %xor
}
define i64 @my_togglebit3(i64 %x) nounwind {
entry:
; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #15)
%x.addr = alloca i64, align 8
store i64 %x, i64* %x.addr, align 8
%0 = load i64, i64* %x.addr, align 8
%xor = xor i64 %0, 32768
ret i64 %xor
}
define i64 @my_togglebit4(i64 %x) nounwind {
entry:
; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #20)
%x.addr = alloca i64, align 8
store i64 %x, i64* %x.addr, align 8
%0 = load i64, i64* %x.addr, align 8
%xor = xor i64 %0, 4503599627370496
ret i64 %xor
}
|
