1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
|
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
; RUN: < %s | FileCheck %s
@c = global i32 4, align 4
@d = global i32 9, align 4
@uc = global i32 4, align 4
@ud = global i32 9, align 4
@b1 = common global i32 0, align 4
; Function Attrs: nounwind
define void @eq() {
entry:
; CHECK-LABEL: .ent eq
%0 = load i32, i32* @c, align 4
%1 = load i32, i32* @d, align 4
%cmp = icmp eq i32 %0, %1
%conv = zext i1 %cmp to i32
; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
; CHECK: xor $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]]
; CHECK: sltiu $[[REG2:[0-9]+]], $[[REG1]], 1
; FIXME: This instruction is redundant. The sltiu can only produce 0 and 1.
; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
store i32 %conv, i32* @b1, align 4
ret void
}
; Function Attrs: nounwind
define void @ne() {
entry:
; CHECK-LABEL: .ent ne
%0 = load i32, i32* @c, align 4
%1 = load i32, i32* @d, align 4
%cmp = icmp ne i32 %0, %1
%conv = zext i1 %cmp to i32
; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
; CHECK: xor $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]]
; CHECK: sltu $[[REG2:[0-9]+]], $zero, $[[REG1]]
; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
store i32 %conv, i32* @b1, align 4
ret void
}
; Function Attrs: nounwind
define void @ugt() {
entry:
; CHECK-LABEL: .ent ugt
%0 = load i32, i32* @uc, align 4
%1 = load i32, i32* @ud, align 4
%cmp = icmp ugt i32 %0, %1
%conv = zext i1 %cmp to i32
; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})
; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}})
; CHECK-DAG: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]])
; CHECK-DAG: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]])
; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UD]], $[[REG_UC]]
; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1
store i32 %conv, i32* @b1, align 4
ret void
}
; Function Attrs: nounwind
define void @ult() {
entry:
; CHECK-LABEL: .ent ult
%0 = load i32, i32* @uc, align 4
%1 = load i32, i32* @ud, align 4
%cmp = icmp ult i32 %0, %1
%conv = zext i1 %cmp to i32
; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})
; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}})
; CHECK-DAG: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]])
; CHECK-DAG: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]])
; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UC]], $[[REG_UD]]
; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1
store i32 %conv, i32* @b1, align 4
ret void
}
; Function Attrs: nounwind
define void @uge() {
entry:
; CHECK-LABEL: .ent uge
%0 = load i32, i32* @uc, align 4
%1 = load i32, i32* @ud, align 4
%cmp = icmp uge i32 %0, %1
%conv = zext i1 %cmp to i32
; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})
; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}})
; CHECK-DAG: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]])
; CHECK-DAG: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]])
; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UC]], $[[REG_UD]]
; CHECK: xori $[[REG2:[0-9]+]], $[[REG1]], 1
; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
store i32 %conv, i32* @b1, align 4
ret void
}
; Function Attrs: nounwind
define void @ule() {
entry:
; CHECK-LABEL: .ent ule
%0 = load i32, i32* @uc, align 4
%1 = load i32, i32* @ud, align 4
%cmp = icmp ule i32 %0, %1
%conv = zext i1 %cmp to i32
; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})
; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}})
; CHECK-DAG: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]])
; CHECK-DAG: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]])
; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UD]], $[[REG_UC]]
; CHECK: xori $[[REG2:[0-9]+]], $[[REG1]], 1
; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
store i32 %conv, i32* @b1, align 4
ret void
}
; Function Attrs: nounwind
define void @sgt() {
entry:
; CHECK-LABEL: .ent sgt
%0 = load i32, i32* @c, align 4
%1 = load i32, i32* @d, align 4
%cmp = icmp sgt i32 %0, %1
%conv = zext i1 %cmp to i32
; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
; CHECK: slt $[[REG1:[0-9]+]], $[[REG_D]], $[[REG_C]]
; FIXME: This instruction is redundant. The slt can only produce 0 and 1.
; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1
store i32 %conv, i32* @b1, align 4
ret void
}
; Function Attrs: nounwind
define void @slt() {
entry:
; CHECK-LABEL: .ent slt
%0 = load i32, i32* @c, align 4
%1 = load i32, i32* @d, align 4
%cmp = icmp slt i32 %0, %1
%conv = zext i1 %cmp to i32
; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
; CHECK: slt $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]]
; FIXME: This instruction is redundant. The slt can only produce 0 and 1.
; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1
store i32 %conv, i32* @b1, align 4
ret void
}
; Function Attrs: nounwind
define void @sge() {
entry:
; CHECK-LABEL: .ent sge
%0 = load i32, i32* @c, align 4
%1 = load i32, i32* @d, align 4
%cmp = icmp sge i32 %0, %1
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @b1, align 4
; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
; CHECK: slt $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]]
; CHECK: xori $[[REG2:[0-9]+]], $[[REG1]], 1
; FIXME: This instruction is redundant. The slt can only produce 0 and 1.
; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
ret void
}
; Function Attrs: nounwind
define void @sle() {
entry:
; CHECK-LABEL: .ent sle
%0 = load i32, i32* @c, align 4
%1 = load i32, i32* @d, align 4
%cmp = icmp sle i32 %0, %1
%conv = zext i1 %cmp to i32
; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
; CHECK: slt $[[REG1:[0-9]+]], $[[REG_D]], $[[REG_C]]
; CHECK: xori $[[REG2:[0-9]+]], $[[REG1]], 1
; FIXME: This instruction is redundant. The slt can only produce 0 and 1.
; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
store i32 %conv, i32* @b1, align 4
ret void
}
|
