1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
|
; Test the handling of base + index + displacement addresses for large frames,
; in cases where both 12-bit and 20-bit displacements are allowed.
; The tests here assume z10 register pressure, without the high words
; being available.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | \
; RUN: FileCheck -check-prefix=CHECK-NOFP %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -disable-fp-elim | \
; RUN: FileCheck -check-prefix=CHECK-FP %s
; This file tests what happens when a displacement is converted from
; being relative to the start of a frame object to being relative to
; the frame itself. In some cases the test is only possible if two
; objects are allocated.
;
; Rather than rely on a particular order for those objects, the tests
; instead allocate two objects of the same size and apply the test to
; both of them. For consistency, all tests follow this model, even if
; one object would actually be enough.
; First check the highest offset that is in range of the 12-bit form.
;
; The last in-range doubleword offset is 4088. Since the frame has two
; emergency spill slots at 160(%r15), the amount that we need to allocate
; in order to put another object at offset 4088 is 4088 - 176 = 3912 bytes.
define void @f1(i8 %byte) {
; CHECK-NOFP-LABEL: f1:
; CHECK-NOFP: stc %r2, 4095(%r15)
; CHECK-NOFP: br %r14
;
; CHECK-FP-LABEL: f1:
; CHECK-FP: stc %r2, 4095(%r11)
; CHECK-FP: br %r14
%region1 = alloca [3912 x i8], align 8
%region2 = alloca [3912 x i8], align 8
%ptr1 = getelementptr inbounds [3912 x i8], [3912 x i8]* %region1, i64 0, i64 7
%ptr2 = getelementptr inbounds [3912 x i8], [3912 x i8]* %region2, i64 0, i64 7
store volatile i8 %byte, i8 *%ptr1
store volatile i8 %byte, i8 *%ptr2
ret void
}
; Test the first offset that is out-of-range of the 12-bit form.
define void @f2(i8 %byte) {
; CHECK-NOFP-LABEL: f2:
; CHECK-NOFP: stcy %r2, 4096(%r15)
; CHECK-NOFP: br %r14
;
; CHECK-FP-LABEL: f2:
; CHECK-FP: stcy %r2, 4096(%r11)
; CHECK-FP: br %r14
%region1 = alloca [3912 x i8], align 8
%region2 = alloca [3912 x i8], align 8
%ptr1 = getelementptr inbounds [3912 x i8], [3912 x i8]* %region1, i64 0, i64 8
%ptr2 = getelementptr inbounds [3912 x i8], [3912 x i8]* %region2, i64 0, i64 8
store volatile i8 %byte, i8 *%ptr1
store volatile i8 %byte, i8 *%ptr2
ret void
}
; Test the last offset that is in range of the 20-bit form.
;
; The last in-range doubleword offset is 524280, so by the same reasoning
; as above, we need to allocate objects of 524280 - 176 = 524104 bytes.
define void @f3(i8 %byte) {
; CHECK-NOFP-LABEL: f3:
; CHECK-NOFP: stcy %r2, 524287(%r15)
; CHECK-NOFP: br %r14
;
; CHECK-FP-LABEL: f3:
; CHECK-FP: stcy %r2, 524287(%r11)
; CHECK-FP: br %r14
%region1 = alloca [524104 x i8], align 8
%region2 = alloca [524104 x i8], align 8
%ptr1 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region1, i64 0, i64 7
%ptr2 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region2, i64 0, i64 7
store volatile i8 %byte, i8 *%ptr1
store volatile i8 %byte, i8 *%ptr2
ret void
}
; Test the first out-of-range offset. We can't use an index register here,
; and the offset is also out of LAY's range, so expect a constant load
; followed by an addition.
define void @f4(i8 %byte) {
; CHECK-NOFP-LABEL: f4:
; CHECK-NOFP: llilh %r1, 8
; CHECK-NOFP: stc %r2, 0(%r1,%r15)
; CHECK-NOFP: br %r14
;
; CHECK-FP-LABEL: f4:
; CHECK-FP: llilh %r1, 8
; CHECK-FP: stc %r2, 0(%r1,%r11)
; CHECK-FP: br %r14
%region1 = alloca [524104 x i8], align 8
%region2 = alloca [524104 x i8], align 8
%ptr1 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region1, i64 0, i64 8
%ptr2 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region2, i64 0, i64 8
store volatile i8 %byte, i8 *%ptr1
store volatile i8 %byte, i8 *%ptr2
ret void
}
; Add 4095 to the previous offset, to test the other end of the STC range.
; The instruction will actually be STCY before frame lowering.
define void @f5(i8 %byte) {
; CHECK-NOFP-LABEL: f5:
; CHECK-NOFP: llilh %r1, 8
; CHECK-NOFP: stc %r2, 4095(%r1,%r15)
; CHECK-NOFP: br %r14
;
; CHECK-FP-LABEL: f5:
; CHECK-FP: llilh %r1, 8
; CHECK-FP: stc %r2, 4095(%r1,%r11)
; CHECK-FP: br %r14
%region1 = alloca [524104 x i8], align 8
%region2 = alloca [524104 x i8], align 8
%ptr1 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region1, i64 0, i64 4103
%ptr2 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region2, i64 0, i64 4103
store volatile i8 %byte, i8 *%ptr1
store volatile i8 %byte, i8 *%ptr2
ret void
}
; Test the next offset after that, which uses STCY instead of STC.
define void @f6(i8 %byte) {
; CHECK-NOFP-LABEL: f6:
; CHECK-NOFP: llilh %r1, 8
; CHECK-NOFP: stcy %r2, 4096(%r1,%r15)
; CHECK-NOFP: br %r14
;
; CHECK-FP-LABEL: f6:
; CHECK-FP: llilh %r1, 8
; CHECK-FP: stcy %r2, 4096(%r1,%r11)
; CHECK-FP: br %r14
%region1 = alloca [524104 x i8], align 8
%region2 = alloca [524104 x i8], align 8
%ptr1 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region1, i64 0, i64 4104
%ptr2 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region2, i64 0, i64 4104
store volatile i8 %byte, i8 *%ptr1
store volatile i8 %byte, i8 *%ptr2
ret void
}
; Now try an offset of 524287 from the start of the object, with the
; object being at offset 1048576 (1 << 20). The backend prefers to create
; anchors 0x10000 bytes apart, so that the high part can be loaded using
; LLILH while still using STC in more cases than 0x40000 anchors would.
define void @f7(i8 %byte) {
; CHECK-NOFP-LABEL: f7:
; CHECK-NOFP: llilh %r1, 23
; CHECK-NOFP: stcy %r2, 65535(%r1,%r15)
; CHECK-NOFP: br %r14
;
; CHECK-FP-LABEL: f7:
; CHECK-FP: llilh %r1, 23
; CHECK-FP: stcy %r2, 65535(%r1,%r11)
; CHECK-FP: br %r14
%region1 = alloca [1048400 x i8], align 8
%region2 = alloca [1048400 x i8], align 8
%ptr1 = getelementptr inbounds [1048400 x i8], [1048400 x i8]* %region1, i64 0, i64 524287
%ptr2 = getelementptr inbounds [1048400 x i8], [1048400 x i8]* %region2, i64 0, i64 524287
store volatile i8 %byte, i8 *%ptr1
store volatile i8 %byte, i8 *%ptr2
ret void
}
; Keep the object-relative offset the same but bump the size of the
; objects by one doubleword.
define void @f8(i8 %byte) {
; CHECK-NOFP-LABEL: f8:
; CHECK-NOFP: llilh %r1, 24
; CHECK-NOFP: stc %r2, 7(%r1,%r15)
; CHECK-NOFP: br %r14
;
; CHECK-FP-LABEL: f8:
; CHECK-FP: llilh %r1, 24
; CHECK-FP: stc %r2, 7(%r1,%r11)
; CHECK-FP: br %r14
%region1 = alloca [1048408 x i8], align 8
%region2 = alloca [1048408 x i8], align 8
%ptr1 = getelementptr inbounds [1048408 x i8], [1048408 x i8]* %region1, i64 0, i64 524287
%ptr2 = getelementptr inbounds [1048408 x i8], [1048408 x i8]* %region2, i64 0, i64 524287
store volatile i8 %byte, i8 *%ptr1
store volatile i8 %byte, i8 *%ptr2
ret void
}
; Check a case where the original displacement is out of range. The backend
; should force separate address logic from the outset. We don't yet do any
; kind of anchor optimization, so there should be no offset on the STC itself.
;
; Before frame lowering this is an LA followed by the AGFI seen below.
; The LA then gets lowered into the LLILH/LA form. The exact sequence
; isn't that important though.
define void @f9(i8 %byte) {
; CHECK-NOFP-LABEL: f9:
; CHECK-NOFP: llilh [[R1:%r[1-5]]], 16
; CHECK-NOFP: la [[R2:%r[1-5]]], 8([[R1]],%r15)
; CHECK-NOFP: agfi [[R2]], 524288
; CHECK-NOFP: stc %r2, 0([[R2]])
; CHECK-NOFP: br %r14
;
; CHECK-FP-LABEL: f9:
; CHECK-FP: llilh [[R1:%r[1-5]]], 16
; CHECK-FP: la [[R2:%r[1-5]]], 8([[R1]],%r11)
; CHECK-FP: agfi [[R2]], 524288
; CHECK-FP: stc %r2, 0([[R2]])
; CHECK-FP: br %r14
%region1 = alloca [1048408 x i8], align 8
%region2 = alloca [1048408 x i8], align 8
%ptr1 = getelementptr inbounds [1048408 x i8], [1048408 x i8]* %region1, i64 0, i64 524288
%ptr2 = getelementptr inbounds [1048408 x i8], [1048408 x i8]* %region2, i64 0, i64 524288
store volatile i8 %byte, i8 *%ptr1
store volatile i8 %byte, i8 *%ptr2
ret void
}
; Repeat f4 in a case that needs the emergency spill slots (because all
; call-clobbered registers are live and no call-saved ones have been
; allocated).
define void @f10(i32 *%vptr, i8 %byte) {
; CHECK-NOFP-LABEL: f10:
; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
; CHECK-NOFP: llilh [[REGISTER]], 8
; CHECK-NOFP: stc %r3, 0([[REGISTER]],%r15)
; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
; CHECK-NOFP: br %r14
;
; CHECK-FP-LABEL: f10:
; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)
; CHECK-FP: llilh [[REGISTER]], 8
; CHECK-FP: stc %r3, 0([[REGISTER]],%r11)
; CHECK-FP: lg [[REGISTER]], [[OFFSET]](%r11)
; CHECK-FP: br %r14
%i0 = load volatile i32 , i32 *%vptr
%i1 = load volatile i32 , i32 *%vptr
%i4 = load volatile i32 , i32 *%vptr
%i5 = load volatile i32 , i32 *%vptr
%region1 = alloca [524104 x i8], align 8
%region2 = alloca [524104 x i8], align 8
%ptr1 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region1, i64 0, i64 8
%ptr2 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region2, i64 0, i64 8
store volatile i8 %byte, i8 *%ptr1
store volatile i8 %byte, i8 *%ptr2
store volatile i32 %i0, i32 *%vptr
store volatile i32 %i1, i32 *%vptr
store volatile i32 %i4, i32 *%vptr
store volatile i32 %i5, i32 *%vptr
ret void
}
; And again with maximum register pressure. The only spill slots that the
; NOFP case needs are the emergency ones, so the offsets are the same as for f4.
; However, the FP case uses %r11 as the frame pointer and must therefore
; spill a second register. This leads to an extra displacement of 8.
define void @f11(i32 *%vptr, i8 %byte) {
; CHECK-NOFP-LABEL: f11:
; CHECK-NOFP: stmg %r6, %r15,
; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
; CHECK-NOFP: llilh [[REGISTER]], 8
; CHECK-NOFP: stc %r3, 0([[REGISTER]],%r15)
; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
; CHECK-NOFP: lmg %r6, %r15,
; CHECK-NOFP: br %r14
;
; CHECK-FP-LABEL: f11:
; CHECK-FP: stmg %r6, %r15,
; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)
; CHECK-FP: llilh [[REGISTER]], 8
; CHECK-FP: stc %r3, 8([[REGISTER]],%r11)
; CHECK-FP: lg [[REGISTER]], [[OFFSET]](%r11)
; CHECK-FP: lmg %r6, %r15,
; CHECK-FP: br %r14
%i0 = load volatile i32 , i32 *%vptr
%i1 = load volatile i32 , i32 *%vptr
%i4 = load volatile i32 , i32 *%vptr
%i5 = load volatile i32 , i32 *%vptr
%i6 = load volatile i32 , i32 *%vptr
%i7 = load volatile i32 , i32 *%vptr
%i8 = load volatile i32 , i32 *%vptr
%i9 = load volatile i32 , i32 *%vptr
%i10 = load volatile i32 , i32 *%vptr
%i11 = load volatile i32 , i32 *%vptr
%i12 = load volatile i32 , i32 *%vptr
%i13 = load volatile i32 , i32 *%vptr
%i14 = load volatile i32 , i32 *%vptr
%region1 = alloca [524104 x i8], align 8
%region2 = alloca [524104 x i8], align 8
%ptr1 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region1, i64 0, i64 8
%ptr2 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region2, i64 0, i64 8
store volatile i8 %byte, i8 *%ptr1
store volatile i8 %byte, i8 *%ptr2
store volatile i32 %i0, i32 *%vptr
store volatile i32 %i1, i32 *%vptr
store volatile i32 %i4, i32 *%vptr
store volatile i32 %i5, i32 *%vptr
store volatile i32 %i6, i32 *%vptr
store volatile i32 %i7, i32 *%vptr
store volatile i32 %i8, i32 *%vptr
store volatile i32 %i9, i32 *%vptr
store volatile i32 %i10, i32 *%vptr
store volatile i32 %i11, i32 *%vptr
store volatile i32 %i12, i32 *%vptr
store volatile i32 %i13, i32 *%vptr
store volatile i32 %i14, i32 *%vptr
ret void
}
; Repeat f4 in a case where the index register is already occupied.
define void @f12(i8 %byte, i64 %index) {
; CHECK-NOFP-LABEL: f12:
; CHECK-NOFP: llilh %r1, 8
; CHECK-NOFP: agr %r1, %r15
; CHECK-NOFP: stc %r2, 0(%r3,%r1)
; CHECK-NOFP: br %r14
;
; CHECK-FP-LABEL: f12:
; CHECK-FP: llilh %r1, 8
; CHECK-FP: agr %r1, %r11
; CHECK-FP: stc %r2, 0(%r3,%r1)
; CHECK-FP: br %r14
%region1 = alloca [524104 x i8], align 8
%region2 = alloca [524104 x i8], align 8
%index1 = add i64 %index, 8
%ptr1 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region1, i64 0, i64 %index1
%ptr2 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region2, i64 0, i64 %index1
store volatile i8 %byte, i8 *%ptr1
store volatile i8 %byte, i8 *%ptr2
ret void
}
|
