1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
|
; Testg 64-bit signed division and remainder.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
; Testg register division. The result is in the second of the two registers.
define void @f1(i64 %dummy, i64 %a, i64 %b, i64 *%dest) {
; CHECK: f1:
; CHECK-NOT: {{%r[234]}}
; CHECK: dsgr %r2, %r4
; CHECK: stg %r3, 0(%r5)
; CHECK: br %r14
%div = sdiv i64 %a, %b
store i64 %div, i64 *%dest
ret void
}
; Testg register remainder. The result is in the first of the two registers.
define void @f2(i64 %dummy, i64 %a, i64 %b, i64 *%dest) {
; CHECK: f2:
; CHECK-NOT: {{%r[234]}}
; CHECK: dsgr %r2, %r4
; CHECK: stg %r2, 0(%r5)
; CHECK: br %r14
%rem = srem i64 %a, %b
store i64 %rem, i64 *%dest
ret void
}
; Testg that division and remainder use a single instruction.
define i64 @f3(i64 %dummy1, i64 %a, i64 %b) {
; CHECK: f3:
; CHECK-NOT: {{%r[234]}}
; CHECK: dsgr %r2, %r4
; CHECK-NOT: dsgr
; CHECK: ogr %r2, %r3
; CHECK: br %r14
%div = sdiv i64 %a, %b
%rem = srem i64 %a, %b
%or = or i64 %rem, %div
ret i64 %or
}
; Testg memory division with no displacement.
define void @f4(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) {
; CHECK: f4:
; CHECK-NOT: {{%r[234]}}
; CHECK: dsg %r2, 0(%r4)
; CHECK: stg %r3, 0(%r5)
; CHECK: br %r14
%b = load i64 *%src
%div = sdiv i64 %a, %b
store i64 %div, i64 *%dest
ret void
}
; Testg memory remainder with no displacement.
define void @f5(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) {
; CHECK: f5:
; CHECK-NOT: {{%r[234]}}
; CHECK: dsg %r2, 0(%r4)
; CHECK: stg %r2, 0(%r5)
; CHECK: br %r14
%b = load i64 *%src
%rem = srem i64 %a, %b
store i64 %rem, i64 *%dest
ret void
}
; Testg both memory division and memory remainder.
define i64 @f6(i64 %dummy, i64 %a, i64 *%src) {
; CHECK: f6:
; CHECK-NOT: {{%r[234]}}
; CHECK: dsg %r2, 0(%r4)
; CHECK-NOT: {{dsg|dsgr}}
; CHECK: ogr %r2, %r3
; CHECK: br %r14
%b = load i64 *%src
%div = sdiv i64 %a, %b
%rem = srem i64 %a, %b
%or = or i64 %rem, %div
ret i64 %or
}
; Check the high end of the DSG range.
define i64 @f7(i64 %dummy, i64 %a, i64 *%src) {
; CHECK: f7:
; CHECK: dsg %r2, 524280(%r4)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 65535
%b = load i64 *%ptr
%rem = srem i64 %a, %b
ret i64 %rem
}
; Check the next doubleword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f8(i64 %dummy, i64 %a, i64 *%src) {
; CHECK: f8:
; CHECK: agfi %r4, 524288
; CHECK: dsg %r2, 0(%r4)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 65536
%b = load i64 *%ptr
%rem = srem i64 %a, %b
ret i64 %rem
}
; Check the high end of the negative aligned DSG range.
define i64 @f9(i64 %dummy, i64 %a, i64 *%src) {
; CHECK: f9:
; CHECK: dsg %r2, -8(%r4)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 -1
%b = load i64 *%ptr
%rem = srem i64 %a, %b
ret i64 %rem
}
; Check the low end of the DSG range.
define i64 @f10(i64 %dummy, i64 %a, i64 *%src) {
; CHECK: f10:
; CHECK: dsg %r2, -524288(%r4)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 -65536
%b = load i64 *%ptr
%rem = srem i64 %a, %b
ret i64 %rem
}
; Check the next doubleword down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f11(i64 %dummy, i64 %a, i64 *%src) {
; CHECK: f11:
; CHECK: agfi %r4, -524296
; CHECK: dsg %r2, 0(%r4)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 -65537
%b = load i64 *%ptr
%rem = srem i64 %a, %b
ret i64 %rem
}
; Check that DSG allows an index.
define i64 @f12(i64 %dummy, i64 %a, i64 %src, i64 %index) {
; CHECK: f12:
; CHECK: dsg %r2, 524287(%r5,%r4)
; CHECK: br %r14
%add1 = add i64 %src, %index
%add2 = add i64 %add1, 524287
%ptr = inttoptr i64 %add2 to i64 *
%b = load i64 *%ptr
%rem = srem i64 %a, %b
ret i64 %rem
}
|
