aboutsummaryrefslogtreecommitdiffstats
path: root/test/CodeGen/SystemZ/risbg-02.ll
blob: 5ccfab028b025fad6b1149f6812db2cc6d15dc41 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
; Test sequences that can use RISBG with a normal first operand.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s

; Test a case with two ANDs.
define i32 @f1(i32 %a, i32 %b) {
; CHECK-LABEL: f1:
; CHECK: risbg %r2, %r3, 60, 62, 0
; CHECK: br %r14
  %anda = and i32 %a, -15
  %andb = and i32 %b, 14
  %or = or i32 %anda, %andb
  ret i32 %or
}

; ...and again with i64.
define i64 @f2(i64 %a, i64 %b) {
; CHECK-LABEL: f2:
; CHECK: risbg %r2, %r3, 60, 62, 0
; CHECK: br %r14
  %anda = and i64 %a, -15
  %andb = and i64 %b, 14
  %or = or i64 %anda, %andb
  ret i64 %or
}

; Test a case with two ANDs and a shift.
define i32 @f3(i32 %a, i32 %b) {
; CHECK-LABEL: f3:
; CHECK: risbg %r2, %r3, 60, 63, 56
; CHECK: br %r14
  %anda = and i32 %a, -16
  %shr = lshr i32 %b, 8
  %andb = and i32 %shr, 15
  %or = or i32 %anda, %andb
  ret i32 %or
}

; ...and again with i64.
define i64 @f4(i64 %a, i64 %b) {
; CHECK-LABEL: f4:
; CHECK: risbg %r2, %r3, 60, 63, 56
; CHECK: br %r14
  %anda = and i64 %a, -16
  %shr = lshr i64 %b, 8
  %andb = and i64 %shr, 15
  %or = or i64 %anda, %andb
  ret i64 %or
}

; Test a case with a single AND and a left shift.
define i32 @f5(i32 %a, i32 %b) {
; CHECK-LABEL: f5:
; CHECK: risbg %r2, %r3, 32, 53, 10
; CHECK: br %r14
  %anda = and i32 %a, 1023
  %shlb = shl i32 %b, 10
  %or = or i32 %anda, %shlb
  ret i32 %or
}

; ...and again with i64.
define i64 @f6(i64 %a, i64 %b) {
; CHECK-LABEL: f6:
; CHECK: risbg %r2, %r3, 0, 53, 10
; CHECK: br %r14
  %anda = and i64 %a, 1023
  %shlb = shl i64 %b, 10
  %or = or i64 %anda, %shlb
  ret i64 %or
}

; Test a case with a single AND and a right shift.
define i32 @f7(i32 %a, i32 %b) {
; CHECK-LABEL: f7:
; CHECK: risbg %r2, %r3, 40, 63, 56
; CHECK: br %r14
  %anda = and i32 %a, -16777216
  %shrb = lshr i32 %b, 8
  %or = or i32 %anda, %shrb
  ret i32 %or
}

; ...and again with i64.
define i64 @f8(i64 %a, i64 %b) {
; CHECK-LABEL: f8:
; CHECK: risbg %r2, %r3, 8, 63, 56
; CHECK: br %r14
  %anda = and i64 %a, -72057594037927936
  %shrb = lshr i64 %b, 8
  %or = or i64 %anda, %shrb
  ret i64 %or
}