1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
|
; Test SETCC for every floating-point condition. The tests here assume that
; RISBLG isn't available.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
; Test CC in { 0 }
define i32 @f1(float %a, float %b) {
; CHECK-LABEL: f1:
; CHECK: ipm %r2
; CHECK-NEXT: afi %r2, -268435456
; CHECK-NEXT: srl %r2, 31
; CHECK: br %r14
%cond = fcmp oeq float %a, %b
%res = zext i1 %cond to i32
ret i32 %res
}
; Test CC in { 1 }
define i32 @f2(float %a, float %b) {
; CHECK-LABEL: f2:
; CHECK: ipm %r2
; CHECK-NEXT: xilf %r2, 268435456
; CHECK-NEXT: afi %r2, -268435456
; CHECK-NEXT: srl %r2, 31
; CHECK: br %r14
%cond = fcmp olt float %a, %b
%res = zext i1 %cond to i32
ret i32 %res
}
; Test CC in { 0, 1 }
define i32 @f3(float %a, float %b) {
; CHECK-LABEL: f3:
; CHECK: ipm %r2
; CHECK-NEXT: afi %r2, -536870912
; CHECK-NEXT: srl %r2, 31
; CHECK: br %r14
%cond = fcmp ole float %a, %b
%res = zext i1 %cond to i32
ret i32 %res
}
; Test CC in { 2 }
define i32 @f4(float %a, float %b) {
; CHECK-LABEL: f4:
; CHECK: ipm %r2
; CHECK-NEXT: xilf %r2, 268435456
; CHECK-NEXT: afi %r2, 1342177280
; CHECK-NEXT: srl %r2, 31
; CHECK: br %r14
%cond = fcmp ogt float %a, %b
%res = zext i1 %cond to i32
ret i32 %res
}
; Test CC in { 0, 2 }
define i32 @f5(float %a, float %b) {
; CHECK-LABEL: f5:
; CHECK: ipm [[REG:%r[0-5]]]
; CHECK-NEXT: xilf [[REG]], 4294967295
; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 36
; CHECK: br %r14
%cond = fcmp oge float %a, %b
%res = zext i1 %cond to i32
ret i32 %res
}
; Test CC in { 1, 2 }
define i32 @f6(float %a, float %b) {
; CHECK-LABEL: f6:
; CHECK: ipm [[REG:%r[0-5]]]
; CHECK-NEXT: afi [[REG]], 268435456
; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 35
; CHECK: br %r14
%cond = fcmp one float %a, %b
%res = zext i1 %cond to i32
ret i32 %res
}
; Test CC in { 0, 1, 2 }
define i32 @f7(float %a, float %b) {
; CHECK-LABEL: f7:
; CHECK: ipm %r2
; CHECK-NEXT: afi %r2, -805306368
; CHECK-NEXT: srl %r2, 31
; CHECK: br %r14
%cond = fcmp ord float %a, %b
%res = zext i1 %cond to i32
ret i32 %res
}
; Test CC in { 3 }
define i32 @f8(float %a, float %b) {
; CHECK-LABEL: f8:
; CHECK: ipm %r2
; CHECK-NEXT: afi %r2, 1342177280
; CHECK-NEXT: srl %r2, 31
; CHECK: br %r14
%cond = fcmp uno float %a, %b
%res = zext i1 %cond to i32
ret i32 %res
}
; Test CC in { 0, 3 }
define i32 @f9(float %a, float %b) {
; CHECK-LABEL: f9:
; CHECK: ipm [[REG:%r[0-5]]]
; CHECK-NEXT: afi [[REG]], -268435456
; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 35
; CHECK: br %r14
%cond = fcmp ueq float %a, %b
%res = zext i1 %cond to i32
ret i32 %res
}
; Test CC in { 1, 3 }
define i32 @f10(float %a, float %b) {
; CHECK-LABEL: f10:
; CHECK: ipm [[REG:%r[0-5]]]
; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 36
; CHECK: br %r14
%cond = fcmp ult float %a, %b
%res = zext i1 %cond to i32
ret i32 %res
}
; Test CC in { 0, 1, 3 }
define i32 @f11(float %a, float %b) {
; CHECK-LABEL: f11:
; CHECK: ipm %r2
; CHECK-NEXT: xilf %r2, 268435456
; CHECK-NEXT: afi %r2, -805306368
; CHECK-NEXT: srl %r2, 31
; CHECK: br %r14
%cond = fcmp ule float %a, %b
%res = zext i1 %cond to i32
ret i32 %res
}
; Test CC in { 2, 3 }
define i32 @f12(float %a, float %b) {
; CHECK-LABEL: f12:
; CHECK: ipm [[REG:%r[0-5]]]
; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 35
; CHECK: br %r14
%cond = fcmp ugt float %a, %b
%res = zext i1 %cond to i32
ret i32 %res
}
; Test CC in { 0, 2, 3 }
define i32 @f13(float %a, float %b) {
; CHECK-LABEL: f13:
; CHECK: ipm %r2
; CHECK-NEXT: xilf %r2, 268435456
; CHECK-NEXT: afi %r2, 1879048192
; CHECK-NEXT: srl %r2, 31
; CHECK: br %r14
%cond = fcmp uge float %a, %b
%res = zext i1 %cond to i32
ret i32 %res
}
; Test CC in { 1, 2, 3 }
define i32 @f14(float %a, float %b) {
; CHECK-LABEL: f14:
; CHECK: ipm %r2
; CHECK-NEXT: afi %r2, 1879048192
; CHECK-NEXT: srl %r2, 31
; CHECK: br %r14
%cond = fcmp une float %a, %b
%res = zext i1 %cond to i32
ret i32 %res
}
|
