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; RUN: llc < %s -march=x86 -mcpu=yonah | FileCheck %s
declare i32 @llvm.cttz.i32(i32, i1)
declare i16 @llvm.ctlz.i16(i16, i1)
declare i32 @llvm.ctlz.i32(i32, i1)
define i32 @cttz_i32(i32 %x) {
%tmp = call i32 @llvm.cttz.i32( i32 %x, i1 true )
ret i32 %tmp
; CHECK: cttz_i32:
; CHECK: bsfl
; CHECK-NOT: cmov
; CHECK: ret
}
define i16 @ctlz_i16(i16 %x, i16 %y) {
entry:
%tmp1 = add i16 %x, %y
%tmp2 = call i16 @llvm.ctlz.i16( i16 %tmp1, i1 true )
ret i16 %tmp2
; CHECK: ctlz_i16:
; CHECK: bsrw
; CHECK-NOT: cmov
; CHECK: xorl $15,
; CHECK: ret
}
define i32 @ctlz_i32(i32 %x) {
%tmp = call i32 @llvm.ctlz.i32( i32 %x, i1 true )
ret i32 %tmp
; CHECK: ctlz_i32:
; CHECK: bsrl
; CHECK-NOT: cmov
; CHECK: xorl $31,
; CHECK: ret
}
define i32 @ctlz_i32_cmov(i32 %n) {
entry:
; Generate a cmov to handle zero inputs when necessary.
; CHECK: ctlz_i32_cmov:
; CHECK: bsrl
; CHECK: cmov
; CHECK: xorl $31,
; CHECK: ret
%tmp1 = call i32 @llvm.ctlz.i32(i32 %n, i1 false)
ret i32 %tmp1
}
define i32 @ctlz_i32_fold_cmov(i32 %n) {
entry:
; Don't generate the cmovne when the source is known non-zero (and bsr would
; not set ZF).
; rdar://9490949
; CHECK: ctlz_i32_fold_cmov:
; CHECK: bsrl
; CHECK-NOT: cmov
; CHECK: xorl $31,
; CHECK: ret
%or = or i32 %n, 1
%tmp1 = call i32 @llvm.ctlz.i32(i32 %or, i1 false)
ret i32 %tmp1
}
define i32 @ctlz_bsr(i32 %n) {
entry:
; Don't generate any xors when a 'ctlz' intrinsic is actually used to compute
; the most significant bit, which is what 'bsr' does natively.
; CHECK: ctlz_bsr:
; CHECK: bsrl
; CHECK-NOT: xorl
; CHECK: ret
%ctlz = call i32 @llvm.ctlz.i32(i32 %n, i1 true)
%bsr = xor i32 %ctlz, 31
ret i32 %bsr
}
define i32 @ctlz_bsr_cmov(i32 %n) {
entry:
; Same as ctlz_bsr, but ensure this happens even when there is a potential
; zero.
; CHECK: ctlz_bsr_cmov:
; CHECK: bsrl
; CHECK-NOT: xorl
; CHECK: ret
%ctlz = call i32 @llvm.ctlz.i32(i32 %n, i1 false)
%bsr = xor i32 %ctlz, 31
ret i32 %bsr
}
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