1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
|
; RUN: llc < %s -march=x86-64 -mcpu=bdver1 | FileCheck %s
; Verify that for the architectures that are known to have poor latency
; double precision shift instructions we generate alternative sequence
; of instructions with lower latencies instead of shld instruction.
;uint64_t lshift1(uint64_t a, uint64_t b)
;{
; return (a << 1) | (b >> 63);
;}
; CHECK: lshift1:
; CHECK: addq {{.*}},{{.*}}
; CHECK-NEXT: shrq $63, {{.*}}
; CHECK-NEXT: leaq ({{.*}},{{.*}}), {{.*}}
define i64 @lshift1(i64 %a, i64 %b) nounwind readnone uwtable {
entry:
%shl = shl i64 %a, 1
%shr = lshr i64 %b, 63
%or = or i64 %shr, %shl
ret i64 %or
}
;uint64_t lshift2(uint64_t a, uint64_t b)
;{
; return (a << 2) | (b >> 62);
;}
; CHECK: lshift2:
; CHECK: shlq $2, {{.*}}
; CHECK-NEXT: shrq $62, {{.*}}
; CHECK-NEXT: leaq ({{.*}},{{.*}}), {{.*}}
define i64 @lshift2(i64 %a, i64 %b) nounwind readnone uwtable {
entry:
%shl = shl i64 %a, 2
%shr = lshr i64 %b, 62
%or = or i64 %shr, %shl
ret i64 %or
}
;uint64_t lshift7(uint64_t a, uint64_t b)
;{
; return (a << 7) | (b >> 57);
;}
; CHECK: lshift7:
; CHECK: shlq $7, {{.*}}
; CHECK-NEXT: shrq $57, {{.*}}
; CHECK-NEXT: leaq ({{.*}},{{.*}}), {{.*}}
define i64 @lshift7(i64 %a, i64 %b) nounwind readnone uwtable {
entry:
%shl = shl i64 %a, 7
%shr = lshr i64 %b, 57
%or = or i64 %shr, %shl
ret i64 %or
}
;uint64_t lshift63(uint64_t a, uint64_t b)
;{
; return (a << 63) | (b >> 1);
;}
; CHECK: lshift63:
; CHECK: shlq $63, {{.*}}
; CHECK-NEXT: shrq {{.*}}
; CHECK-NEXT: leaq ({{.*}},{{.*}}), {{.*}}
define i64 @lshift63(i64 %a, i64 %b) nounwind readnone uwtable {
entry:
%shl = shl i64 %a, 63
%shr = lshr i64 %b, 1
%or = or i64 %shr, %shl
ret i64 %or
}
|
