1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
|
; RUN: opt < %s -S -inline -inline-threshold=2 | FileCheck %s
; RUN: opt < %s -S -strip-debug -inline -inline-threshold=2 | FileCheck %s
;
; The purpose of this test is to check that debug info doesn't influence
; inlining decisions.
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
declare void @llvm.dbg.declare(metadata, metadata, metadata) #1
declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1
define <4 x float> @inner_vectors(<4 x float> %a, <4 x float> %b) {
entry:
call void @llvm.dbg.value(metadata !{}, i64 0, metadata !{}, metadata !{})
%mul = fmul <4 x float> %a, <float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00>
call void @llvm.dbg.value(metadata !{}, i64 0, metadata !{}, metadata !{})
%mul1 = fmul <4 x float> %b, <float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00>
call void @llvm.dbg.value(metadata !{}, i64 0, metadata !{}, metadata !{})
%add = fadd <4 x float> %mul, %mul1
ret <4 x float> %add
}
define float @outer_vectors(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: @outer_vectors(
; CHECK-NOT: call <4 x float> @inner_vectors(
; CHECK: ret float
entry:
call void @llvm.dbg.value(metadata !{}, i64 0, metadata !{}, metadata !{})
call void @llvm.dbg.value(metadata !{}, i64 0, metadata !{}, metadata !{})
%call = call <4 x float> @inner_vectors(<4 x float> %a, <4 x float> %b)
call void @llvm.dbg.value(metadata !{}, i64 0, metadata !{}, metadata !{})
%vecext = extractelement <4 x float> %call, i32 0
%vecext1 = extractelement <4 x float> %call, i32 1
%add = fadd float %vecext, %vecext1
%vecext2 = extractelement <4 x float> %call, i32 2
%add3 = fadd float %add, %vecext2
%vecext4 = extractelement <4 x float> %call, i32 3
%add5 = fadd float %add3, %vecext4
ret float %add5
}
attributes #0 = { nounwind readnone }
!llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!3, !4}
!llvm.ident = !{!5}
!0 = !{!"0x11\004\00\000\00\000\00\000", !1, !2, !2, !{}, !2, !2} ; [ DW_TAG_compile_unit ]
!1 = !{!"", !""}
!2 = !{i32 0}
!3 = !{i32 2, !"Dwarf Version", i32 4}
!4 = !{i32 1, !"Debug Info Version", i32 2}
!5 = !{!""}
|
