1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
|
; RUN: opt < %s -simplifycfg -S | FileCheck %s
declare void @foo1()
declare void @foo2()
define void @test1(i32 %V) {
%C1 = icmp eq i32 %V, 4 ; <i1> [#uses=1]
%C2 = icmp eq i32 %V, 17 ; <i1> [#uses=1]
%CN = or i1 %C1, %C2 ; <i1> [#uses=1]
br i1 %CN, label %T, label %F
T: ; preds = %0
call void @foo1( )
ret void
F: ; preds = %0
call void @foo2( )
ret void
; CHECK: @test1
; CHECK: switch i32 %V, label %F [
; CHECK: i32 17, label %T
; CHECK: i32 4, label %T
; CHECK: ]
}
define void @test2(i32 %V) {
%C1 = icmp ne i32 %V, 4 ; <i1> [#uses=1]
%C2 = icmp ne i32 %V, 17 ; <i1> [#uses=1]
%CN = and i1 %C1, %C2 ; <i1> [#uses=1]
br i1 %CN, label %T, label %F
T: ; preds = %0
call void @foo1( )
ret void
F: ; preds = %0
call void @foo2( )
ret void
; CHECK: @test2
; CHECK: switch i32 %V, label %T [
; CHECK: i32 17, label %F
; CHECK: i32 4, label %F
; CHECK: ]
}
define void @test3(i32 %V) {
%C1 = icmp eq i32 %V, 4 ; <i1> [#uses=1]
br i1 %C1, label %T, label %N
N: ; preds = %0
%C2 = icmp eq i32 %V, 17 ; <i1> [#uses=1]
br i1 %C2, label %T, label %F
T: ; preds = %N, %0
call void @foo1( )
ret void
F: ; preds = %N
call void @foo2( )
ret void
; CHECK: @test3
; CHECK: switch i32 %V, label %F [
; CHECK: i32 4, label %T
; CHECK: i32 17, label %T
; CHECK: ]
}
define i32 @test4(i8 zeroext %c) nounwind ssp noredzone {
entry:
%cmp = icmp eq i8 %c, 62
br i1 %cmp, label %lor.end, label %lor.lhs.false
lor.lhs.false: ; preds = %entry
%cmp4 = icmp eq i8 %c, 34
br i1 %cmp4, label %lor.end, label %lor.rhs
lor.rhs: ; preds = %lor.lhs.false
%cmp8 = icmp eq i8 %c, 92
br label %lor.end
lor.end: ; preds = %lor.rhs, %lor.lhs.false, %entry
%0 = phi i1 [ true, %lor.lhs.false ], [ true, %entry ], [ %cmp8, %lor.rhs ]
%lor.ext = zext i1 %0 to i32
ret i32 %lor.ext
; CHECK: @test4
; CHECK: switch i8 %c, label %lor.rhs [
; CHECK: i8 62, label %lor.end
; CHECK: i8 34, label %lor.end
; CHECK: i8 92, label %lor.end
; CHECK: ]
}
define i32 @test5(i8 zeroext %c) nounwind ssp noredzone {
entry:
switch i8 %c, label %lor.rhs [
i8 62, label %lor.end
i8 34, label %lor.end
i8 92, label %lor.end
]
lor.rhs: ; preds = %entry
%V = icmp eq i8 %c, 92
br label %lor.end
lor.end: ; preds = %entry, %entry, %entry, %lor.rhs
%0 = phi i1 [ true, %entry ], [ %V, %lor.rhs ], [ true, %entry ], [ true, %entry ]
%lor.ext = zext i1 %0 to i32
ret i32 %lor.ext
; CHECK: @test5
; CHECK: switch i8 %c, label %lor.rhs [
; CHECK: i8 62, label %lor.end
; CHECK: i8 34, label %lor.end
; CHECK: i8 92, label %lor.end
; CHECK: ]
}
define i1 @test6({ i32, i32 }* %I) {
entry:
%tmp.1.i = getelementptr { i32, i32 }* %I, i64 0, i32 1 ; <i32*> [#uses=1]
%tmp.2.i = load i32* %tmp.1.i ; <i32> [#uses=6]
%tmp.2 = icmp eq i32 %tmp.2.i, 14 ; <i1> [#uses=1]
br i1 %tmp.2, label %shortcirc_done.4, label %shortcirc_next.0
shortcirc_next.0: ; preds = %entry
%tmp.6 = icmp eq i32 %tmp.2.i, 15 ; <i1> [#uses=1]
br i1 %tmp.6, label %shortcirc_done.4, label %shortcirc_next.1
shortcirc_next.1: ; preds = %shortcirc_next.0
%tmp.11 = icmp eq i32 %tmp.2.i, 16 ; <i1> [#uses=1]
br i1 %tmp.11, label %shortcirc_done.4, label %shortcirc_next.2
shortcirc_next.2: ; preds = %shortcirc_next.1
%tmp.16 = icmp eq i32 %tmp.2.i, 17 ; <i1> [#uses=1]
br i1 %tmp.16, label %shortcirc_done.4, label %shortcirc_next.3
shortcirc_next.3: ; preds = %shortcirc_next.2
%tmp.21 = icmp eq i32 %tmp.2.i, 18 ; <i1> [#uses=1]
br i1 %tmp.21, label %shortcirc_done.4, label %shortcirc_next.4
shortcirc_next.4: ; preds = %shortcirc_next.3
%tmp.26 = icmp eq i32 %tmp.2.i, 19 ; <i1> [#uses=1]
br label %UnifiedReturnBlock
shortcirc_done.4: ; preds = %shortcirc_next.3, %shortcirc_next.2, %shortcirc_next.1, %shortcirc_next.0, %entry
br label %UnifiedReturnBlock
UnifiedReturnBlock: ; preds = %shortcirc_done.4, %shortcirc_next.4
%UnifiedRetVal = phi i1 [ %tmp.26, %shortcirc_next.4 ], [ true, %shortcirc_done.4 ] ; <i1> [#uses=1]
ret i1 %UnifiedRetVal
; CHECK: @test6
; CHECK: %tmp.2.i.off = add i32 %tmp.2.i, -14
; CHECK: %switch = icmp ult i32 %tmp.2.i.off, 6
}
define void @test7(i8 zeroext %c, i32 %x) nounwind ssp noredzone {
entry:
%cmp = icmp ult i32 %x, 32
%cmp4 = icmp eq i8 %c, 97
%or.cond = or i1 %cmp, %cmp4
%cmp9 = icmp eq i8 %c, 99
%or.cond11 = or i1 %or.cond, %cmp9
br i1 %or.cond11, label %if.then, label %if.end
if.then: ; preds = %entry
tail call void @foo1() nounwind noredzone
ret void
if.end: ; preds = %entry
ret void
; CHECK: @test7
; CHECK: %cmp = icmp ult i32 %x, 32
; CHECK: br i1 %cmp, label %if.then, label %switch.early.test
; CHECK: switch.early.test:
; CHECK: switch i8 %c, label %if.end [
; CHECK: i8 99, label %if.then
; CHECK: i8 97, label %if.then
; CHECK: ]
}
define i32 @test8(i8 zeroext %c, i32 %x, i1 %C) nounwind ssp noredzone {
entry:
br i1 %C, label %N, label %if.then
N:
%cmp = icmp ult i32 %x, 32
%cmp4 = icmp eq i8 %c, 97
%or.cond = or i1 %cmp, %cmp4
%cmp9 = icmp eq i8 %c, 99
%or.cond11 = or i1 %or.cond, %cmp9
br i1 %or.cond11, label %if.then, label %if.end
if.then: ; preds = %entry
%A = phi i32 [0, %entry], [42, %N]
tail call void @foo1() nounwind noredzone
ret i32 %A
if.end: ; preds = %entry
ret i32 0
; CHECK: @test8
; CHECK: switch.early.test:
; CHECK: switch i8 %c, label %if.end [
; CHECK: i8 99, label %if.then
; CHECK: i8 97, label %if.then
; CHECK: ]
; CHECK: %A = phi i32 [ 0, %entry ], [ 42, %switch.early.test ], [ 42, %N ], [ 42, %switch.early.test ]
}
;; This is "Example 7" from http://blog.regehr.org/archives/320
define i32 @test9(i8 zeroext %c) nounwind ssp noredzone {
entry:
%cmp = icmp ult i8 %c, 33
br i1 %cmp, label %lor.end, label %lor.lhs.false
lor.lhs.false: ; preds = %entry
%cmp4 = icmp eq i8 %c, 46
br i1 %cmp4, label %lor.end, label %lor.lhs.false6
lor.lhs.false6: ; preds = %lor.lhs.false
%cmp9 = icmp eq i8 %c, 44
br i1 %cmp9, label %lor.end, label %lor.lhs.false11
lor.lhs.false11: ; preds = %lor.lhs.false6
%cmp14 = icmp eq i8 %c, 58
br i1 %cmp14, label %lor.end, label %lor.lhs.false16
lor.lhs.false16: ; preds = %lor.lhs.false11
%cmp19 = icmp eq i8 %c, 59
br i1 %cmp19, label %lor.end, label %lor.lhs.false21
lor.lhs.false21: ; preds = %lor.lhs.false16
%cmp24 = icmp eq i8 %c, 60
br i1 %cmp24, label %lor.end, label %lor.lhs.false26
lor.lhs.false26: ; preds = %lor.lhs.false21
%cmp29 = icmp eq i8 %c, 62
br i1 %cmp29, label %lor.end, label %lor.lhs.false31
lor.lhs.false31: ; preds = %lor.lhs.false26
%cmp34 = icmp eq i8 %c, 34
br i1 %cmp34, label %lor.end, label %lor.lhs.false36
lor.lhs.false36: ; preds = %lor.lhs.false31
%cmp39 = icmp eq i8 %c, 92
br i1 %cmp39, label %lor.end, label %lor.rhs
lor.rhs: ; preds = %lor.lhs.false36
%cmp43 = icmp eq i8 %c, 39
br label %lor.end
lor.end: ; preds = %lor.rhs, %lor.lhs.false36, %lor.lhs.false31, %lor.lhs.false26, %lor.lhs.false21, %lor.lhs.false16, %lor.lhs.false11, %lor.lhs.false6, %lor.lhs.false, %entry
%0 = phi i1 [ true, %lor.lhs.false36 ], [ true, %lor.lhs.false31 ], [ true, %lor.lhs.false26 ], [ true, %lor.lhs.false21 ], [ true, %lor.lhs.false16 ], [ true, %lor.lhs.false11 ], [ true, %lor.lhs.false6 ], [ true, %lor.lhs.false ], [ true, %entry ], [ %cmp43, %lor.rhs ]
%conv46 = zext i1 %0 to i32
ret i32 %conv46
; CHECK: @test9
; CHECK: %cmp = icmp ult i8 %c, 33
; CHECK: br i1 %cmp, label %lor.end, label %switch.early.test
; CHECK: switch.early.test:
; CHECK: switch i8 %c, label %lor.rhs [
; CHECK: i8 92, label %lor.end
; CHECK: i8 62, label %lor.end
; CHECK: i8 60, label %lor.end
; CHECK: i8 59, label %lor.end
; CHECK: i8 58, label %lor.end
; CHECK: i8 46, label %lor.end
; CHECK: i8 44, label %lor.end
; CHECK: i8 34, label %lor.end
; CHECK: i8 39, label %lor.end
; CHECK: ]
}
define i32 @test10(i32 %mode, i1 %Cond) {
%A = icmp ne i32 %mode, 0
%B = icmp ne i32 %mode, 51
%C = and i1 %A, %B
%D = and i1 %C, %Cond
br i1 %D, label %T, label %F
T:
ret i32 123
F:
ret i32 324
; CHECK: @test10
; CHECK: br i1 %Cond, label %switch.early.test, label %F
; CHECK:switch.early.test:
; CHECK: switch i32 %mode, label %T [
; CHECK: i32 51, label %F
; CHECK: i32 0, label %F
; CHECK: ]
}
; PR8780
define i32 @test11(i32 %bar) nounwind {
entry:
%cmp = icmp eq i32 %bar, 4
%cmp2 = icmp eq i32 %bar, 35
%or.cond = or i1 %cmp, %cmp2
%cmp5 = icmp eq i32 %bar, 53
%or.cond1 = or i1 %or.cond, %cmp5
%cmp8 = icmp eq i32 %bar, 24
%or.cond2 = or i1 %or.cond1, %cmp8
%cmp11 = icmp eq i32 %bar, 23
%or.cond3 = or i1 %or.cond2, %cmp11
%cmp14 = icmp eq i32 %bar, 55
%or.cond4 = or i1 %or.cond3, %cmp14
%cmp17 = icmp eq i32 %bar, 12
%or.cond5 = or i1 %or.cond4, %cmp17
%cmp20 = icmp eq i32 %bar, 35
%or.cond6 = or i1 %or.cond5, %cmp20
br i1 %or.cond6, label %if.then, label %if.end
if.then: ; preds = %entry
br label %return
if.end: ; preds = %entry
br label %return
return: ; preds = %if.end, %if.then
%retval.0 = phi i32 [ 1, %if.then ], [ 0, %if.end ]
ret i32 %retval.0
; CHECK: @test11
; CHECK: switch i32 %bar, label %if.end [
; CHECK: i32 55, label %return
; CHECK: i32 53, label %return
; CHECK: i32 35, label %return
; CHECK: i32 24, label %return
; CHECK: i32 23, label %return
; CHECK: i32 12, label %return
; CHECK: i32 4, label %return
; CHECK: ]
}
define void @test12() nounwind {
entry:
br label %bb49.us.us
bb49.us.us:
%A = icmp eq i32 undef, undef
br i1 %A, label %bb55.us.us, label %malformed
bb48.us.us:
%B = icmp ugt i32 undef, undef
br i1 %B, label %bb55.us.us, label %bb49.us.us
bb55.us.us:
br label %bb48.us.us
malformed:
ret void
; CHECK: @test12
}
; test13 - handle switch formation with ult.
define void @test13(i32 %x) nounwind ssp noredzone {
entry:
%cmp = icmp ult i32 %x, 2
br i1 %cmp, label %if.then, label %lor.lhs.false3
lor.lhs.false3: ; preds = %lor.lhs.false
%cmp5 = icmp eq i32 %x, 3
br i1 %cmp5, label %if.then, label %lor.lhs.false6
lor.lhs.false6: ; preds = %lor.lhs.false3
%cmp8 = icmp eq i32 %x, 4
br i1 %cmp8, label %if.then, label %lor.lhs.false9
lor.lhs.false9: ; preds = %lor.lhs.false6
%cmp11 = icmp eq i32 %x, 6
br i1 %cmp11, label %if.then, label %if.end
if.then: ; preds = %lor.lhs.false9, %lor.lhs.false6, %lor.lhs.false3, %lor.lhs.false, %entry
call void @foo1() noredzone
br label %if.end
if.end: ; preds = %if.then, %lor.lhs.false9
ret void
; CHECK: @test13
; CHECK: switch i32 %x, label %if.end [
; CHECK: i32 6, label %if.then
; CHECK: i32 4, label %if.then
; CHECK: i32 3, label %if.then
; CHECK: i32 1, label %if.then
; CHECK: i32 0, label %if.then
; CHECK: ]
}
; test14 - handle switch formation with ult.
define void @test14(i32 %x) nounwind ssp noredzone {
entry:
%cmp = icmp ugt i32 %x, 2
br i1 %cmp, label %lor.lhs.false3, label %if.then
lor.lhs.false3: ; preds = %lor.lhs.false
%cmp5 = icmp ne i32 %x, 3
br i1 %cmp5, label %lor.lhs.false6, label %if.then
lor.lhs.false6: ; preds = %lor.lhs.false3
%cmp8 = icmp ne i32 %x, 4
br i1 %cmp8, label %lor.lhs.false9, label %if.then
lor.lhs.false9: ; preds = %lor.lhs.false6
%cmp11 = icmp ne i32 %x, 6
br i1 %cmp11, label %if.end, label %if.then
if.then: ; preds = %lor.lhs.false9, %lor.lhs.false6, %lor.lhs.false3, %lor.lhs.false, %entry
call void @foo1() noredzone
br label %if.end
if.end: ; preds = %if.then, %lor.lhs.false9
ret void
; CHECK: @test14
; CHECK: switch i32 %x, label %if.end [
; CHECK: i32 6, label %if.then
; CHECK: i32 4, label %if.then
; CHECK: i32 3, label %if.then
; CHECK: i32 1, label %if.then
; CHECK: i32 0, label %if.then
; CHECK: ]
}
; Don't crash on ginormous ranges.
define void @test15(i128 %x) nounwind {
%cmp = icmp ugt i128 %x, 2
br i1 %cmp, label %if.end, label %lor.false
lor.false:
%cmp2 = icmp ne i128 %x, 100000000000000000000
br i1 %cmp2, label %if.end, label %if.then
if.then:
call void @foo1() noredzone
br label %if.end
if.end:
ret void
; CHECK: @test15
; CHECK-NOT: switch
; CHECK: ret void
}
; PR8675
; rdar://5134905
define zeroext i1 @test16(i32 %x) nounwind {
entry:
; CHECK: @test16
; CHECK: %x.off = add i32 %x, -1
; CHECK: %switch = icmp ult i32 %x.off, 3
%cmp.i = icmp eq i32 %x, 1
br i1 %cmp.i, label %lor.end, label %lor.lhs.false
lor.lhs.false:
%cmp.i2 = icmp eq i32 %x, 2
br i1 %cmp.i2, label %lor.end, label %lor.rhs
lor.rhs:
%cmp.i1 = icmp eq i32 %x, 3
br label %lor.end
lor.end:
%0 = phi i1 [ true, %lor.lhs.false ], [ true, %entry ], [ %cmp.i1, %lor.rhs ]
ret i1 %0
}
; Check that we don't turn an icmp into a switch where it's not useful.
define void @test17(i32 %x, i32 %y) {
%cmp = icmp ult i32 %x, 3
%switch = icmp ult i32 %y, 2
%or.cond775 = or i1 %cmp, %switch
br i1 %or.cond775, label %lor.lhs.false8, label %return
lor.lhs.false8:
tail call void @foo1()
ret void
return:
ret void
; CHECK: @test17
; CHECK-NOT: switch.early.test
; CHECK-NOT: switch i32
; CHECK: ret void
}
|
