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| author | Jason Ekstrand <jason.ekstrand@intel.com> | 2014-10-06 21:27:06 -0700 |
|---|---|---|
| committer | Jason Ekstrand <jason.ekstrand@intel.com> | 2014-10-24 16:24:05 -0700 |
| commit | 2ec161b2396b08341264965a5825152784b54549 (patch) | |
| tree | b1ecc9bc9ac7987d6cc6540a74e9acb7578d3573 | |
| parent | ee65f2b50d5a411e05fb4e0dbe26766a47305b59 (diff) | |
| download | external_mesa3d-2ec161b2396b08341264965a5825152784b54549.zip external_mesa3d-2ec161b2396b08341264965a5825152784b54549.tar.gz external_mesa3d-2ec161b2396b08341264965a5825152784b54549.tar.bz2 | |
i965/fs: Don't interfere with too many base registers
On older GENs in SIMD16 mode, we were accidentally building too much
interference into our register classes. Since everything is divided by 2,
the reigster allocator thinks we have 64 base registers instead of 128.
The actual GRF mapping still needs to be doubled, but as far as the ra_set
is concerned, we only have 64. We were accidentally adding way too much
interference.
Signed-off-by: Jason Ekstrand <jason.ekstrand@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp index 34ee40f..0c4888f 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp @@ -179,8 +179,8 @@ brw_alloc_reg_set(struct intel_screen *screen, int reg_width) ra_reg_to_grf[reg] = j * 2; - for (int base_reg = j * 2; - base_reg < j * 2 + class_sizes[i]; + for (int base_reg = j; + base_reg < j + (class_sizes[i] + 1) / 2; base_reg++) { ra_add_transitive_reg_conflict(regs, base_reg, reg); } |