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| author | Marek Olšák <marek.olsak@amd.com> | 2016-10-25 21:47:52 +0200 |
|---|---|---|
| committer | Emil Velikov <emil.l.velikov@gmail.com> | 2016-11-01 12:49:02 +0000 |
| commit | 2ec8ad91b3d27d8f2fca813ce18ea7eb7b66b106 (patch) | |
| tree | a19078a9b59800950bb541e062a0362038e22a10 | |
| parent | 0ff597c39b7330bef99fd76d0a2db5c1d8e7fb85 (diff) | |
| download | external_mesa3d-2ec8ad91b3d27d8f2fca813ce18ea7eb7b66b106.zip external_mesa3d-2ec8ad91b3d27d8f2fca813ce18ea7eb7b66b106.tar.gz external_mesa3d-2ec8ad91b3d27d8f2fca813ce18ea7eb7b66b106.tar.bz2 | |
radeonsi: set VGT_GS_ONCHIP_CNTL on CIK and later
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Cc: 11.2 12.0 13.0 <mesa-stable@lists.freedesktop.org>
(cherry picked from commit e24dc4316487eeaa6ee8aa5c709546d814e96f03)
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 97bd308..85747eb 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -3925,6 +3925,14 @@ static void si_init_config(struct si_context *sctx) si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0); if (sctx->b.chip_class >= CIK) { + /* If this is 0, Bonaire can hang even if GS isn't being used. + * Other chips are unaffected. These are suboptimal values, + * but we don't use on-chip GS. + */ + si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL, + S_028A44_ES_VERTS_PER_SUBGRP(64) | + S_028A44_GS_PRIMS_PER_SUBGRP(4)); + si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff)); si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0); si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff)); |