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| author | Francisco Jerez <currojerez@riseup.net> | 2015-11-26 16:42:43 +0200 |
|---|---|---|
| committer | Francisco Jerez <currojerez@riseup.net> | 2015-12-09 13:46:05 +0200 |
| commit | 353abb294b10aa18bf98a772b380ccbed318c239 (patch) | |
| tree | f3e0069a6814b9974a69b24c39d58c99285907c5 | |
| parent | fa043698d2f6c2e4b6a4993dfeab8f0d00c33e77 (diff) | |
| download | external_mesa3d-353abb294b10aa18bf98a772b380ccbed318c239.zip external_mesa3d-353abb294b10aa18bf98a772b380ccbed318c239.tar.gz external_mesa3d-353abb294b10aa18bf98a772b380ccbed318c239.tar.bz2 | |
i965: Define and use REG_MASK macro to make masked MMIO writes slightly more readable.
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_defines.h | 6 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_state_upload.c | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_l3_state.c | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_reg.h | 2 |
4 files changed, 9 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 97ef6d4..ba6290d 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -41,6 +41,12 @@ #define GET_BITS(data, high, low) ((data & INTEL_MASK((high), (low))) >> (low)) #define GET_FIELD(word, field) (((word) & field ## _MASK) >> field ## _SHIFT) +/** + * For use with masked MMIO registers where the upper 16 bits control which + * of the lower bits are committed to the register. + */ +#define REG_MASK(value) ((value) << 16) + #ifndef BRW_DEFINES_H #define BRW_DEFINES_H diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index 750eb75..58be242 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -387,7 +387,7 @@ brw_upload_initial_gpu_state(struct brw_context *brw) BEGIN_BATCH(3); OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2)); OUT_BATCH(GEN7_CACHE_MODE_1); - OUT_BATCH((GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC << 16) | + OUT_BATCH(REG_MASK(GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC) | GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC); ADVANCE_BATCH(); } diff --git a/src/mesa/drivers/dri/i965/gen7_l3_state.c b/src/mesa/drivers/dri/i965/gen7_l3_state.c index 141d481..05bc7aa 100644 --- a/src/mesa/drivers/dri/i965/gen7_l3_state.c +++ b/src/mesa/drivers/dri/i965/gen7_l3_state.c @@ -268,7 +268,7 @@ setup_l3_config(struct brw_context *brw, const struct brw_l3_config *cfg) OUT_BATCH(HSW_SCRATCH1); OUT_BATCH(has_dc ? 0 : HSW_SCRATCH1_L3_ATOMIC_DISABLE); OUT_BATCH(HSW_ROW_CHICKEN3); - OUT_BATCH(HSW_ROW_CHICKEN3_L3_ATOMIC_DISABLE << 16 | + OUT_BATCH(REG_MASK(HSW_ROW_CHICKEN3_L3_ATOMIC_DISABLE) | (has_dc ? 0 : HSW_ROW_CHICKEN3_L3_ATOMIC_DISABLE)); ADVANCE_BATCH(); } diff --git a/src/mesa/drivers/dri/i965/intel_reg.h b/src/mesa/drivers/dri/i965/intel_reg.h index 0b167d5..8888d6f 100644 --- a/src/mesa/drivers/dri/i965/intel_reg.h +++ b/src/mesa/drivers/dri/i965/intel_reg.h @@ -183,7 +183,7 @@ # define GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE (1 << 13) # define GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC (1 << 1) # define GEN8_HIZ_PMA_MASK_BITS \ - ((GEN8_HIZ_NP_PMA_FIX_ENABLE | GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE) << 16) + REG_MASK(GEN8_HIZ_NP_PMA_FIX_ENABLE | GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE) /* Predicate registers */ #define MI_PREDICATE_SRC0 0x2400 |