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| author | Nicolai Hähnle <nicolai.haehnle@amd.com> | 2016-09-12 16:27:41 +0200 |
|---|---|---|
| committer | Nicolai Hähnle <nicolai.haehnle@amd.com> | 2016-09-27 16:45:41 +0200 |
| commit | 4421c0fb0dc7a51c3d639c452ad8a5d55a99cec1 (patch) | |
| tree | fe8256b9fcf727432e2696a08ccf8c8f4cb86faf | |
| parent | fb827c055cb1bdd2b18d0687c06c56b537d805f3 (diff) | |
| download | external_mesa3d-4421c0fb0dc7a51c3d639c452ad8a5d55a99cec1.zip external_mesa3d-4421c0fb0dc7a51c3d639c452ad8a5d55a99cec1.tar.gz external_mesa3d-4421c0fb0dc7a51c3d639c452ad8a5d55a99cec1.tar.bz2 | |
gallium/radeon/winsyses: reduce the number of pb_cache buckets
Small buffers are now handled via the slabs code, so separate buckets in
pb_cache have become redundant.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
| -rw-r--r-- | src/gallium/auxiliary/pipebuffer/pb_cache.h | 2 | ||||
| -rw-r--r-- | src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 6 | ||||
| -rw-r--r-- | src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 6 |
3 files changed, 5 insertions, 9 deletions
diff --git a/src/gallium/auxiliary/pipebuffer/pb_cache.h b/src/gallium/auxiliary/pipebuffer/pb_cache.h index aa83cc8..7000fcd 100644 --- a/src/gallium/auxiliary/pipebuffer/pb_cache.h +++ b/src/gallium/auxiliary/pipebuffer/pb_cache.h @@ -50,7 +50,7 @@ struct pb_cache /* The cache is divided into buckets for minimizing cache misses. * The driver controls which buffer goes into which bucket. */ - struct list_head buckets[8]; + struct list_head buckets[4]; pipe_mutex mutex; uint64_t cache_size; diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c index c13dc2b..e8d2c00 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c @@ -741,12 +741,10 @@ no_slab: /* Determine the pb_cache bucket for minimizing pb_cache misses. */ pb_cache_bucket = 0; - if (size <= 4096) /* small buffers */ - pb_cache_bucket += 1; if (domain & RADEON_DOMAIN_VRAM) /* VRAM or VRAM+GTT */ - pb_cache_bucket += 2; + pb_cache_bucket += 1; if (flags == RADEON_FLAG_GTT_WC) /* WC */ - pb_cache_bucket += 4; + pb_cache_bucket += 2; assert(pb_cache_bucket < ARRAY_SIZE(ws->bo_cache.buckets)); /* Get a buffer from the cache. */ diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c index 3af01f8..5818006 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c @@ -1014,12 +1014,10 @@ no_slab: /* Determine the pb_cache bucket for minimizing pb_cache misses. */ pb_cache_bucket = 0; - if (size <= 4096) /* small buffers */ - pb_cache_bucket += 1; if (domain & RADEON_DOMAIN_VRAM) /* VRAM or VRAM+GTT */ - pb_cache_bucket += 2; + pb_cache_bucket += 1; if (flags == RADEON_FLAG_GTT_WC) /* WC */ - pb_cache_bucket += 4; + pb_cache_bucket += 2; assert(pb_cache_bucket < ARRAY_SIZE(ws->bo_cache.buckets)); bo = radeon_bo(pb_cache_reclaim_buffer(&ws->bo_cache, size, alignment, |