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| author | Michel Dänzer <michel.daenzer@amd.com> | 2013-03-12 12:34:37 +0100 |
|---|---|---|
| committer | Michel Dänzer <michel@daenzer.net> | 2013-03-12 18:25:54 +0100 |
| commit | 4dca602521c51a4cb03855bda9c22b5ccc4829c7 (patch) | |
| tree | 03c37af616896e64b46f924ef3debf248b701f84 | |
| parent | 8aa8b0539eda00b9bafacb69774b26975db66ae4 (diff) | |
| download | external_mesa3d-4dca602521c51a4cb03855bda9c22b5ccc4829c7.zip external_mesa3d-4dca602521c51a4cb03855bda9c22b5ccc4829c7.tar.gz external_mesa3d-4dca602521c51a4cb03855bda9c22b5ccc4829c7.tar.bz2 | |
radeonsi: Fix off-by-one for maximum vertex element index in some cases
In cases where the vertex element size is smaller than the vertex buffer
stride, the previous calculation could end up 1 too low. This would result
in the GPU using index 0 instead of the maximum index for those elements,
which would be visible as intermittent distorted triangles.
NOTE: This is a candidate for the 9.1 branch.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state_draw.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index f8460b0..1049d2b 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -448,8 +448,14 @@ static void si_vertex_buffer_update(struct r600_context *rctx) si_pm4_sh_data_add(pm4, va & 0xFFFFFFFF); si_pm4_sh_data_add(pm4, (S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(vb->stride))); - si_pm4_sh_data_add(pm4, (vb->buffer->width0 - vb->buffer_offset) / - MAX2(vb->stride, 1)); + if (vb->stride) + /* Round up by rounding down and adding 1 */ + si_pm4_sh_data_add(pm4, + (vb->buffer->width0 - offset - + util_format_get_blocksize(ve->src_format)) / + vb->stride + 1); + else + si_pm4_sh_data_add(pm4, vb->buffer->width0 - offset); si_pm4_sh_data_add(pm4, rctx->vertex_elements->rsrc_word3[i]); if (!bound[ve->vertex_buffer_index]) { |