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| author | Tom Stellard <thomas.stellard@amd.com> | 2012-08-23 19:27:48 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2012-08-23 21:54:32 +0000 |
| commit | 5a1edb8655aeab17bf0d90e202fb31a1adb53498 (patch) | |
| tree | 36ae701132e8da585b1fc8dc7c1ccfb6bcb47680 | |
| parent | cb5227b403a9c78a734e5e67657da6c485881cbb (diff) | |
| download | external_mesa3d-5a1edb8655aeab17bf0d90e202fb31a1adb53498.zip external_mesa3d-5a1edb8655aeab17bf0d90e202fb31a1adb53498.tar.gz external_mesa3d-5a1edb8655aeab17bf0d90e202fb31a1adb53498.tar.bz2 | |
radeon/llvm: Simplify the convert to ISA pass
| -rw-r--r-- | src/gallium/drivers/radeon/AMDGPUConvertToISA.cpp | 11 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp | 14 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/AMDGPUInstrInfo.h | 2 |
3 files changed, 7 insertions, 20 deletions
diff --git a/src/gallium/drivers/radeon/AMDGPUConvertToISA.cpp b/src/gallium/drivers/radeon/AMDGPUConvertToISA.cpp index b876a66..fbca0a7 100644 --- a/src/gallium/drivers/radeon/AMDGPUConvertToISA.cpp +++ b/src/gallium/drivers/radeon/AMDGPUConvertToISA.cpp @@ -52,15 +52,10 @@ bool AMDGPUConvertToISAPass::runOnMachineFunction(MachineFunction &MF) for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end(); BB != BB_E; ++BB) { MachineBasicBlock &MBB = *BB; - for (MachineBasicBlock::iterator I = MBB.begin(), Next = llvm::next(I); - I != MBB.end(); I = Next, Next = llvm::next(I) ) { + for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); + I != E; ++I) { MachineInstr &MI = *I; - MachineInstr * newInstr = TII->convertToISA(MI, MF, MBB.findDebugLoc(I)); - if (!newInstr) { - continue; - } - MBB.insert(I, newInstr); - MI.eraseFromParent(); + TII->convertToISA(MI, MF, MBB.findDebugLoc(I)); } } return false; diff --git a/src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp b/src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp index 03a647e..9aae09a 100644 --- a/src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp +++ b/src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp @@ -27,7 +27,7 @@ using namespace llvm; AMDGPUInstrInfo::AMDGPUInstrInfo(TargetMachine &tm) - : AMDGPUGenInstrInfo(), RI(tm, *this), TM(tm) { } + : AMDGPUGenInstrInfo(0,0), RI(tm, *this), TM(tm) { } const AMDGPURegisterInfo &AMDGPUInstrInfo::getRegisterInfo() const { return RI; @@ -234,17 +234,13 @@ AMDGPUInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { // TODO: Implement this function return true; } - -MachineInstr * AMDGPUInstrInfo::convertToISA(MachineInstr & MI, MachineFunction &MF, + +void AMDGPUInstrInfo::convertToISA(MachineInstr & MI, MachineFunction &MF, DebugLoc DL) const { - MachineInstrBuilder newInstr; MachineRegisterInfo &MRI = MF.getRegInfo(); const AMDGPURegisterInfo & RI = getRegisterInfo(); - // Create the new instruction - newInstr = BuildMI(MF, DL, TM.getInstrInfo()->get(MI.getOpcode())); - for (unsigned i = 0; i < MI.getNumOperands(); i++) { MachineOperand &MO = MI.getOperand(i); // Convert dst regclass to one that is supported by the ISA @@ -258,9 +254,5 @@ MachineInstr * AMDGPUInstrInfo::convertToISA(MachineInstr & MI, MachineFunction MRI.setRegClass(MO.getReg(), newRegClass); } } - // Add the operand to the new instruction - newInstr.addOperand(MO); } - - return newInstr; } diff --git a/src/gallium/drivers/radeon/AMDGPUInstrInfo.h b/src/gallium/drivers/radeon/AMDGPUInstrInfo.h index dd5108e..2643119 100644 --- a/src/gallium/drivers/radeon/AMDGPUInstrInfo.h +++ b/src/gallium/drivers/radeon/AMDGPUInstrInfo.h @@ -138,7 +138,7 @@ public: /// convertToISA - Convert the AMDIL MachineInstr to a supported ISA /// MachineInstr - virtual MachineInstr * convertToISA(MachineInstr & MI, MachineFunction &MF, + virtual void convertToISA(MachineInstr & MI, MachineFunction &MF, DebugLoc DL) const; }; |