r600g: convert sampler view emission into atoms

Vertex and constant buffers are emitted in the same way.
This is mainly a simplification of the code. The cleanup is in another patch.

6 files changed, 238 insertions, 134 deletions

diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index d4e9fae..8f037e2 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -956,7 +956,6 @@ static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_conte
 {
 	struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
 	struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
-	struct r600_pipe_resource_state *rstate;
 	struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
 	unsigned format, endian;
 	uint32_t word4 = 0, yuv_format = 0, pitch = 0;
@@ -966,7 +965,6 @@ static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_conte
 
 	if (view == NULL)
 		return NULL;
-	rstate = &view->state;
 
 	/* initialize base object */
 	view->base = *state;
@@ -1058,44 +1056,39 @@ static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_conte
 		depth = texture->array_size;
 	}
 
-	rstate->bo[0] = &tmp->resource;
-	rstate->bo[1] = &tmp->resource;
-	rstate->bo_usage[0] = RADEON_USAGE_READ;
-	rstate->bo_usage[1] = RADEON_USAGE_READ;
-
-	rstate->val[0] = (S_030000_DIM(r600_tex_dim(texture->target)) |
-			  S_030000_PITCH((pitch / 8) - 1) |
-			  S_030000_TEX_WIDTH(width - 1));
+	view->tex_resource = &tmp->resource;
+	view->tex_resource_words[0] = (S_030000_DIM(r600_tex_dim(texture->target)) |
+				       S_030000_PITCH((pitch / 8) - 1) |
+				       S_030000_TEX_WIDTH(width - 1));
 	if (rscreen->chip_class == CAYMAN)
-		rstate->val[0] |= CM_S_030000_NON_DISP_TILING_ORDER(tile_type);
+		view->tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(tile_type);
 	else
-		rstate->val[0] |= S_030000_NON_DISP_TILING_ORDER(tile_type);
-	rstate->val[1] = (S_030004_TEX_HEIGHT(height - 1) |
-			  S_030004_TEX_DEPTH(depth - 1) |
-			  S_030004_ARRAY_MODE(array_mode));
-	rstate->val[2] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
+		view->tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(tile_type);
+	view->tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
+				       S_030004_TEX_DEPTH(depth - 1) |
+				       S_030004_ARRAY_MODE(array_mode));
+	view->tex_resource_words[2] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
 	if (state->u.tex.last_level) {
-		rstate->val[3] = (tmp->offset[1] + r600_resource_va(ctx->screen, texture)) >> 8;
+		view->tex_resource_words[3] = (tmp->offset[1] + r600_resource_va(ctx->screen, texture)) >> 8;
 	} else {
-		rstate->val[3] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
-	}
-	rstate->val[4] = (word4 |
-			  S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
-			  S_030010_ENDIAN_SWAP(endian) |
-			  S_030010_BASE_LEVEL(state->u.tex.first_level));
-	rstate->val[5] = (S_030014_LAST_LEVEL(state->u.tex.last_level) |
-			  S_030014_BASE_ARRAY(state->u.tex.first_layer) |
-			  S_030014_LAST_ARRAY(state->u.tex.last_layer));
+		view->tex_resource_words[3] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
+	}
+	view->tex_resource_words[4] = (word4 |
+				       S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
+				       S_030010_ENDIAN_SWAP(endian) |
+				       S_030010_BASE_LEVEL(state->u.tex.first_level));
+	view->tex_resource_words[5] = (S_030014_LAST_LEVEL(state->u.tex.last_level) |
+				       S_030014_BASE_ARRAY(state->u.tex.first_layer) |
+				       S_030014_LAST_ARRAY(state->u.tex.last_layer));
 	/* aniso max 16 samples */
-	rstate->val[6] = (S_030018_MAX_ANISO(4)) |
-			 (S_030018_TILE_SPLIT(tile_split));
-	rstate->val[7] = S_03001C_DATA_FORMAT(format) |
-			 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
-			 S_03001C_BANK_WIDTH(bankw) |
-			 S_03001C_BANK_HEIGHT(bankh) |
-			 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
-			 S_03001C_NUM_BANKS(nbanks);
-
+	view->tex_resource_words[6] = (S_030018_MAX_ANISO(4)) |
+				      (S_030018_TILE_SPLIT(tile_split));
+	view->tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
+				      S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
+				      S_03001C_BANK_WIDTH(bankw) |
+				      S_03001C_BANK_HEIGHT(bankh) |
+				      S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
+				      S_03001C_NUM_BANKS(nbanks);
 	return &view->base;
 }
 
@@ -1103,16 +1096,14 @@ static void evergreen_set_vs_sampler_views(struct pipe_context *ctx, unsigned co
 					   struct pipe_sampler_view **views)
 {
 	struct r600_context *rctx = (struct r600_context *)ctx;
-	r600_set_sampler_views(rctx, &rctx->vs_samplers, count, views,
-			       r600_context_pipe_state_set_vs_resource);
+	r600_set_sampler_views(rctx, &rctx->vs_samplers, count, views);
 }
 
 static void evergreen_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
 					   struct pipe_sampler_view **views)
 {
 	struct r600_context *rctx = (struct r600_context *)ctx;
-	r600_set_sampler_views(rctx, &rctx->ps_samplers, count, views,
-			       r600_context_pipe_state_set_ps_resource);
+	r600_set_sampler_views(rctx, &rctx->ps_samplers, count, views);
 }
 
 static void evergreen_bind_samplers(struct r600_context *rctx,
@@ -1856,6 +1847,46 @@ static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct
 				       R_028940_ALU_CONST_CACHE_PS_0);
 }
 
+static void evergreen_emit_sampler_views(struct r600_context *rctx,
+					 struct r600_samplerview_state *state,
+					 unsigned resource_id_base)
+{
+	struct radeon_winsys_cs *cs = rctx->cs;
+	uint32_t dirty_mask = state->dirty_mask;
+
+	while (dirty_mask) {
+		struct r600_pipe_sampler_view *rview;
+		unsigned resource_index = u_bit_scan(&dirty_mask);
+		unsigned reloc;
+
+		rview = state->views[resource_index];
+		assert(rview);
+
+		r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
+		r600_write_value(cs, (resource_id_base + resource_index) * 8);
+		r600_write_array(cs, 8, rview->tex_resource_words);
+
+		/* XXX The kernel needs two relocations. This is stupid. */
+		reloc = r600_context_bo_reloc(rctx, rview->tex_resource,
+					      RADEON_USAGE_READ);
+		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
+		r600_write_value(cs, reloc);
+		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
+		r600_write_value(cs, reloc);
+	}
+	state->dirty_mask = 0;
+}
+
+static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
+{
+	evergreen_emit_sampler_views(rctx, &rctx->vs_samplers.views, 176 + R600_MAX_CONST_BUFFERS);
+}
+
+static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
+{
+	evergreen_emit_sampler_views(rctx, &rctx->ps_samplers.views, R600_MAX_CONST_BUFFERS);
+}
+
 void evergreen_init_state_functions(struct r600_context *rctx)
 {
 	r600_init_atom(&rctx->cb_misc_state.atom, evergreen_emit_cb_misc_state, 0, 0);
@@ -1866,6 +1897,8 @@ void evergreen_init_state_functions(struct r600_context *rctx)
 	r600_init_atom(&rctx->cs_vertex_buffer_state.atom, evergreen_cs_emit_vertex_buffers, 0, 0);
 	r600_init_atom(&rctx->vs_constbuf_state.atom, evergreen_emit_vs_constant_buffers, 0, 0);
 	r600_init_atom(&rctx->ps_constbuf_state.atom, evergreen_emit_ps_constant_buffers, 0, 0);
+	r600_init_atom(&rctx->vs_samplers.views.atom, evergreen_emit_vs_sampler_views, 0, 0);
+	r600_init_atom(&rctx->ps_samplers.views.atom, evergreen_emit_ps_sampler_views, 0, 0);
 
 	rctx->context.create_blend_state = evergreen_create_blend_state;
 	rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c
index 7679012..9429a1b 100644
--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -74,8 +74,8 @@ static void r600_blitter_begin(struct pipe_context *ctx, enum r600_blitter_op op
 			(void**)rctx->ps_samplers.samplers);
 
 		util_blitter_save_fragment_sampler_views(
-			rctx->blitter, rctx->ps_samplers.n_views,
-			(struct pipe_sampler_view**)rctx->ps_samplers.views);
+			rctx->blitter, util_last_bit(rctx->ps_samplers.views.enabled_mask),
+			(struct pipe_sampler_view**)rctx->ps_samplers.views.views);
 	}
 
 	if ((op & R600_DISABLE_RENDER_COND) && rctx->current_render_cond) {
@@ -184,7 +184,7 @@ void r600_blit_uncompress_depth(struct pipe_context *ctx,
 }
 
 void r600_flush_depth_textures(struct r600_context *rctx,
-			       struct r600_textures_info *textures)
+			       struct r600_samplerview_state *textures)
 {
 	unsigned i;
 	unsigned depth_texture_mask = textures->depth_texture_mask;
diff --git a/src/gallium/drivers/r600/r600_hw_context.c b/src/gallium/drivers/r600/r600_hw_context.c
index d0a5918..bf93d41 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -1289,6 +1289,11 @@ void r600_context_flush(struct r600_context *ctx, unsigned flags)
 	r600_constant_buffers_dirty(ctx, &ctx->vs_constbuf_state);
 	r600_constant_buffers_dirty(ctx, &ctx->ps_constbuf_state);
 
+	ctx->vs_samplers.views.dirty_mask = ctx->vs_samplers.views.enabled_mask;
+	ctx->ps_samplers.views.dirty_mask = ctx->ps_samplers.views.enabled_mask;
+	r600_sampler_views_dirty(ctx, &ctx->vs_samplers.views);
+	r600_sampler_views_dirty(ctx, &ctx->ps_samplers.views);
+
 	if (streamout_suspended) {
 		ctx->streamout_start = TRUE;
 		ctx->streamout_append_bitmask = ~0;
diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h
index 0b45314..22e3664 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -153,7 +153,8 @@ struct r600_screen {
 
 struct r600_pipe_sampler_view {
 	struct pipe_sampler_view	base;
-	struct r600_pipe_resource_state		state;
+	struct r600_resource		*tex_resource;
+	uint32_t			tex_resource_words[8];
 };
 
 struct r600_pipe_rasterizer {
@@ -234,11 +235,19 @@ struct r600_pipe_sampler_state {
 /* needed for blitter save */
 #define NUM_TEX_UNITS 16
 
-struct r600_textures_info {
+struct r600_samplerview_state
+{
+	struct r600_atom		atom;
 	struct r600_pipe_sampler_view	*views[NUM_TEX_UNITS];
-	struct r600_pipe_sampler_state	*samplers[NUM_TEX_UNITS];
-	unsigned			n_views;
+	uint32_t			enabled_mask;
+	uint32_t			dirty_mask;
 	uint32_t			depth_texture_mask; /* which textures are depth */
+};
+
+struct r600_textures_info {
+	struct r600_samplerview_state	views;
+
+	struct r600_pipe_sampler_state	*samplers[NUM_TEX_UNITS];
 	unsigned			n_samplers;
 	bool				samplers_dirty;
 	bool				is_array_sampler[NUM_TEX_UNITS];
@@ -325,8 +334,6 @@ struct r600_context {
 	unsigned			alpha_ref;
 	boolean				alpha_ref_dirty;
 	unsigned			nr_cbufs;
-	struct r600_textures_info	vs_samplers;
-	struct r600_textures_info	ps_samplers;
 
 	struct u_upload_mgr	        *uploader;
 	struct util_slab_mempool	pool_transfers;
@@ -349,6 +356,8 @@ struct r600_context {
 	struct r600_vertexbuf_state	cs_vertex_buffer_state;
 	struct r600_constbuf_state	vs_constbuf_state;
 	struct r600_constbuf_state	ps_constbuf_state;
+	struct r600_textures_info	vs_samplers;
+	struct r600_textures_info	ps_samplers;
 
 	struct radeon_winsys_cs	*cs;
 
@@ -452,7 +461,7 @@ void r600_blit_uncompress_depth(struct pipe_context *ctx,
 		unsigned first_level, unsigned last_level,
 		unsigned first_layer, unsigned last_layer);
 void r600_flush_depth_textures(struct r600_context *rctx,
-			       struct r600_textures_info *textures);
+			       struct r600_samplerview_state *textures);
 /* r600_buffer.c */
 bool r600_init_resource(struct r600_screen *rscreen,
 			struct r600_resource *res,
@@ -528,11 +537,12 @@ void r600_set_index_buffer(struct pipe_context *ctx,
 void r600_vertex_buffers_dirty(struct r600_context *rctx);
 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
 			     const struct pipe_vertex_buffer *input);
+void r600_sampler_views_dirty(struct r600_context *rctx,
+			      struct r600_samplerview_state *state);
 void r600_set_sampler_views(struct r600_context *rctx,
 			    struct r600_textures_info *dst,
 			    unsigned count,
-			    struct pipe_sampler_view **views,
-			    void (*set_resource)(struct r600_context*, struct r600_pipe_resource_state*, unsigned));
+			    struct pipe_sampler_view **views);
 void *r600_create_vertex_elements(struct pipe_context *ctx,
 				  unsigned count,
 				  const struct pipe_vertex_element *elements);
@@ -707,6 +717,13 @@ static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value)
 	cs->buf[cs->cdw++] = value;
 }
 
+static INLINE void r600_write_array(struct radeon_winsys_cs *cs, unsigned num, unsigned *ptr)
+{
+	assert(cs->cdw+num <= RADEON_MAX_CMDBUF_DWORDS);
+	memcpy(&cs->buf[cs->cdw], ptr, num * sizeof(ptr[0]));
+	cs->cdw += num;
+}
+
 static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 {
 	assert(reg < R600_CONTEXT_REG_OFFSET);
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 508b6c6..e14aeac 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -974,7 +974,6 @@ static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *c
 {
 	struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
 	struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
-	struct r600_pipe_resource_state *rstate;
 	struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
 	unsigned format, endian;
 	uint32_t word4 = 0, yuv_format = 0, pitch = 0;
@@ -983,7 +982,6 @@ static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *c
 
 	if (view == NULL)
 		return NULL;
-	rstate = &view->state;
 
 	/* initialize base object */
 	view->base = *state;
@@ -1037,31 +1035,27 @@ static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *c
 			depth = texture->array_size;
 		}
 
-		rstate->bo[0] = &tmp->resource;
-		rstate->bo[1] = &tmp->resource;
-		rstate->bo_usage[0] = RADEON_USAGE_READ;
-		rstate->bo_usage[1] = RADEON_USAGE_READ;
-
-		rstate->val[0] = (S_038000_DIM(r600_tex_dim(texture->target)) |
-				S_038000_TILE_MODE(array_mode) |
-				S_038000_TILE_TYPE(tile_type) |
-				S_038000_PITCH((pitch / 8) - 1) |
-				S_038000_TEX_WIDTH(width - 1));
-		rstate->val[1] = (S_038004_TEX_HEIGHT(height - 1) |
-				S_038004_TEX_DEPTH(depth - 1) |
-				S_038004_DATA_FORMAT(format));
-		rstate->val[2] = tmp->offset[offset_level] >> 8;
-		rstate->val[3] = tmp->offset[offset_level+1] >> 8;
-		rstate->val[4] = (word4 |
-				S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
-				S_038010_REQUEST_SIZE(1) |
-				S_038010_ENDIAN_SWAP(endian) |
-				S_038010_BASE_LEVEL(0));
-		rstate->val[5] = (S_038014_LAST_LEVEL(last_level) |
-				S_038014_BASE_ARRAY(state->u.tex.first_layer) |
-				S_038014_LAST_ARRAY(state->u.tex.last_layer));
-		rstate->val[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
-				S_038018_MAX_ANISO(4 /* max 16 samples */));
+		view->tex_resource = &tmp->resource;
+		view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target)) |
+					       S_038000_TILE_MODE(array_mode) |
+					       S_038000_TILE_TYPE(tile_type) |
+					       S_038000_PITCH((pitch / 8) - 1) |
+					       S_038000_TEX_WIDTH(width - 1));
+		view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
+					       S_038004_TEX_DEPTH(depth - 1) |
+					       S_038004_DATA_FORMAT(format));
+		view->tex_resource_words[2] = tmp->offset[offset_level] >> 8;
+		view->tex_resource_words[3] = tmp->offset[offset_level+1] >> 8;
+		view->tex_resource_words[4] = (word4 |
+					       S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
+					       S_038010_REQUEST_SIZE(1) |
+					       S_038010_ENDIAN_SWAP(endian) |
+					       S_038010_BASE_LEVEL(0));
+		view->tex_resource_words[5] = (S_038014_LAST_LEVEL(last_level) |
+					       S_038014_BASE_ARRAY(state->u.tex.first_layer) |
+					       S_038014_LAST_ARRAY(state->u.tex.last_layer));
+		view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
+					       S_038018_MAX_ANISO(4 /* max 16 samples */));
 	} else {
 		width = tmp->surface.level[offset_level].npix_x;
 		height = tmp->surface.level[offset_level].npix_y;
@@ -1091,35 +1085,31 @@ static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *c
 			break;
 		}
 
-		rstate->bo[0] = &tmp->resource;
-		rstate->bo[1] = &tmp->resource;
-		rstate->bo_usage[0] = RADEON_USAGE_READ;
-		rstate->bo_usage[1] = RADEON_USAGE_READ;
-
-		rstate->val[0] = (S_038000_DIM(r600_tex_dim(texture->target)) |
-				S_038000_TILE_MODE(array_mode) |
-				S_038000_TILE_TYPE(tile_type) |
-				S_038000_PITCH((pitch / 8) - 1) |
-				S_038000_TEX_WIDTH(width - 1));
-		rstate->val[1] = (S_038004_TEX_HEIGHT(height - 1) |
-				S_038004_TEX_DEPTH(depth - 1) |
-				S_038004_DATA_FORMAT(format));
-		rstate->val[2] = tmp->surface.level[offset_level].offset >> 8;
+		view->tex_resource = &tmp->resource;
+		view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target)) |
+					       S_038000_TILE_MODE(array_mode) |
+					       S_038000_TILE_TYPE(tile_type) |
+					       S_038000_PITCH((pitch / 8) - 1) |
+					       S_038000_TEX_WIDTH(width - 1));
+		view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
+					       S_038004_TEX_DEPTH(depth - 1) |
+					       S_038004_DATA_FORMAT(format));
+		view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8;
 		if (offset_level >= tmp->surface.last_level) {
-			rstate->val[3] = tmp->surface.level[offset_level].offset >> 8;
+			view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8;
 		} else {
-			rstate->val[3] = tmp->surface.level[offset_level + 1].offset >> 8;
+			view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
 		}
-		rstate->val[4] = (word4 |
-				S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
-				S_038010_REQUEST_SIZE(1) |
-				S_038010_ENDIAN_SWAP(endian) |
-				S_038010_BASE_LEVEL(0));
-		rstate->val[5] = (S_038014_LAST_LEVEL(last_level) |
-				S_038014_BASE_ARRAY(state->u.tex.first_layer) |
-				S_038014_LAST_ARRAY(state->u.tex.last_layer));
-		rstate->val[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
-				S_038018_MAX_ANISO(4 /* max 16 samples */));
+		view->tex_resource_words[4] = (word4 |
+					       S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
+					       S_038010_REQUEST_SIZE(1) |
+					       S_038010_ENDIAN_SWAP(endian) |
+					       S_038010_BASE_LEVEL(0));
+		view->tex_resource_words[5] = (S_038014_LAST_LEVEL(last_level) |
+					       S_038014_BASE_ARRAY(state->u.tex.first_layer) |
+					       S_038014_LAST_ARRAY(state->u.tex.last_layer));
+		view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
+					       S_038018_MAX_ANISO(4 /* max 16 samples */));
 	}
 	return &view->base;
 }
@@ -1128,16 +1118,14 @@ static void r600_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
 				      struct pipe_sampler_view **views)
 {
 	struct r600_context *rctx = (struct r600_context *)ctx;
-	r600_set_sampler_views(rctx, &rctx->vs_samplers, count, views,
-			       r600_context_pipe_state_set_vs_resource);
+	r600_set_sampler_views(rctx, &rctx->vs_samplers, count, views);
 }
 
 static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
 				      struct pipe_sampler_view **views)
 {
 	struct r600_context *rctx = (struct r600_context *)ctx;
-	r600_set_sampler_views(rctx, &rctx->ps_samplers, count, views,
-			       r600_context_pipe_state_set_ps_resource);
+	r600_set_sampler_views(rctx, &rctx->ps_samplers, count, views);
 }
 
 static void r600_set_seamless_cubemap(struct r600_context *rctx, boolean enable)
@@ -1195,9 +1183,9 @@ static void r600_update_samplers(struct r600_context *rctx,
 			/* TEX_ARRAY_OVERRIDE must be set for array textures to disable
 			 * filtering between layers.
 			 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view. */
-			if (tex->views[i]) {
-				if (tex->views[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
-				    tex->views[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) {
+			if (tex->views.views[i]) {
+				if (tex->views.views[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
+				    tex->views.views[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) {
 					tex->samplers[i]->rstate.regs[0].value |= S_03C000_TEX_ARRAY_OVERRIDE(1);
 					tex->is_array_sampler[i] = true;
 				} else {
@@ -1796,6 +1784,46 @@ static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600
 				   R_028940_ALU_CONST_CACHE_PS_0);
 }
 
+static void r600_emit_sampler_views(struct r600_context *rctx,
+				    struct r600_samplerview_state *state,
+				    unsigned resource_id_base)
+{
+	struct radeon_winsys_cs *cs = rctx->cs;
+	uint32_t dirty_mask = state->dirty_mask;
+
+	while (dirty_mask) {
+		struct r600_pipe_sampler_view *rview;
+		unsigned resource_index = u_bit_scan(&dirty_mask);
+		unsigned reloc;
+
+		rview = state->views[resource_index];
+		assert(rview);
+
+		r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
+		r600_write_value(cs, (resource_id_base + resource_index) * 7);
+		r600_write_array(cs, 7, rview->tex_resource_words);
+
+		/* XXX The kernel needs two relocations. This is stupid. */
+		reloc = r600_context_bo_reloc(rctx, rview->tex_resource,
+					      RADEON_USAGE_READ);
+		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
+		r600_write_value(cs, reloc);
+		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
+		r600_write_value(cs, reloc);
+	}
+	state->dirty_mask = 0;
+}
+
+static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
+{
+	r600_emit_sampler_views(rctx, &rctx->vs_samplers.views, 160 + R600_MAX_CONST_BUFFERS);
+}
+
+static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
+{
+	r600_emit_sampler_views(rctx, &rctx->ps_samplers.views, R600_MAX_CONST_BUFFERS);
+}
+
 void r600_init_state_functions(struct r600_context *rctx)
 {
 	r600_init_atom(&rctx->cb_misc_state.atom, r600_emit_cb_misc_state, 0, 0);
@@ -1805,6 +1833,8 @@ void r600_init_state_functions(struct r600_context *rctx)
 	r600_init_atom(&rctx->vertex_buffer_state.atom, r600_emit_vertex_buffers, 0, 0);
 	r600_init_atom(&rctx->vs_constbuf_state.atom, r600_emit_vs_constant_buffers, 0, 0);
 	r600_init_atom(&rctx->ps_constbuf_state.atom, r600_emit_ps_constant_buffers, 0, 0);
+	r600_init_atom(&rctx->vs_samplers.views.atom, r600_emit_vs_sampler_views, 0, 0);
+	r600_init_atom(&rctx->ps_samplers.views.atom, r600_emit_ps_sampler_views, 0, 0);
 
 	rctx->context.create_blend_state = r600_create_blend_state;
 	rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c
index f1d5d57..eda8d4e 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -457,20 +457,41 @@ void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
 	r600_vertex_buffers_dirty(rctx);
 }
 
+void r600_sampler_views_dirty(struct r600_context *rctx,
+			      struct r600_samplerview_state *state)
+{
+	if (state->dirty_mask) {
+		r600_inval_texture_cache(rctx);
+		state->atom.num_dw = (rctx->chip_class >= EVERGREEN ? 14 : 13) *
+				     util_bitcount(state->dirty_mask);
+		r600_atom_dirty(rctx, &state->atom);
+	}
+}
+
 void r600_set_sampler_views(struct r600_context *rctx,
 			    struct r600_textures_info *dst,
 			    unsigned count,
-			    struct pipe_sampler_view **views,
-			    void (*set_resource)(struct r600_context*, struct r600_pipe_resource_state*, unsigned))
+			    struct pipe_sampler_view **views)
 {
 	struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
 	unsigned i;
+	/* This sets 1-bit for textures with index >= count. */
+	uint32_t disable_mask = ~((1ull << count) - 1);
+	/* These are the new textures set by this function. */
+	uint32_t new_mask = 0;
 
-	if (count)
-		r600_inval_texture_cache(rctx);
+	/* Set textures with index >= count to NULL. */
+	uint32_t remaining_mask = dst->views.enabled_mask & disable_mask;
+
+	while (remaining_mask) {
+		i = u_bit_scan(&remaining_mask);
+		assert(dst->views.views[i]);
+
+		pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
+	}
 
 	for (i = 0; i < count; i++) {
-		if (rviews[i] == dst->views[i]) {
+		if (rviews[i] == dst->views.views[i]) {
 			continue;
 		}
 
@@ -479,9 +500,9 @@ void r600_set_sampler_views(struct r600_context *rctx,
 				(struct r600_resource_texture*)rviews[i]->base.texture;
 
 			if (rtex->is_depth && !rtex->is_flushing_texture) {
-				dst->depth_texture_mask |= 1 << i;
+				dst->views.depth_texture_mask |= 1 << i;
 			} else {
-				dst->depth_texture_mask &= ~(1 << i);
+				dst->views.depth_texture_mask &= ~(1 << i);
 			}
 
 			/* Changing from array to non-arrays textures and vice
@@ -492,23 +513,21 @@ void r600_set_sampler_views(struct r600_context *rctx,
 				dst->samplers_dirty = true;
 			}
 
-			set_resource(rctx, &rviews[i]->state, i + R600_MAX_CONST_BUFFERS);
+			pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], views[i]);
+			new_mask |= 1 << i;
 		} else {
-			set_resource(rctx, NULL, i + R600_MAX_CONST_BUFFERS);
-			dst->depth_texture_mask &= ~(1 << i);
+			pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
+			disable_mask |= 1 << i;
 		}
-
-		pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views[i], views[i]);
 	}
 
-	for (i = count; i < dst->n_views; i++) {
-		if (dst->views[i]) {
-			set_resource(rctx, NULL, i + R600_MAX_CONST_BUFFERS);
-			pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views[i], NULL);
-		}
-	}
+	dst->views.enabled_mask &= ~disable_mask;
+	dst->views.dirty_mask &= dst->views.enabled_mask;
+	dst->views.enabled_mask |= new_mask;
+	dst->views.dirty_mask |= new_mask;
+	dst->views.depth_texture_mask &= dst->views.enabled_mask;
 
-	dst->n_views = count;
+	r600_sampler_views_dirty(rctx, &dst->views);
 }
 
 void *r600_create_vertex_elements(struct pipe_context *ctx,
@@ -902,11 +921,11 @@ static void r600_update_derived_state(struct r600_context *rctx)
 
 	if (!rctx->blitter->running) {
 		/* Flush depth textures which need to be flushed. */
-		if (rctx->vs_samplers.depth_texture_mask) {
-			r600_flush_depth_textures(rctx, &rctx->vs_samplers);
+		if (rctx->vs_samplers.views.depth_texture_mask) {
+			r600_flush_depth_textures(rctx, &rctx->vs_samplers.views);
 		}
-		if (rctx->ps_samplers.depth_texture_mask) {
-			r600_flush_depth_textures(rctx, &rctx->ps_samplers);
+		if (rctx->ps_samplers.views.depth_texture_mask) {
+			r600_flush_depth_textures(rctx, &rctx->ps_samplers.views);
 		}
 	}