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authorKenneth Graunke <kenneth@whitecape.org>2014-07-26 13:12:37 -0700
committerKenneth Graunke <kenneth@whitecape.org>2014-08-02 05:16:40 -0700
commit7679393f561ca4f0e9c9587d4b208b035b7b9098 (patch)
treec4251cccc885439e3e3812df28b49b1e212bc408
parenta50b640dfe3580049e07bfdafb2e69410844359d (diff)
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i965: Make brw_update_sampler_state use 8 bits for LOD fields on Gen7+.
This was the only actual difference between Gen4-6 and Gen7+ in terms of the values we program. The rest was just mechanical structure rearrangement. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
-rw-r--r--src/mesa/drivers/dri/i965/brw_sampler_state.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_sampler_state.c b/src/mesa/drivers/dri/i965/brw_sampler_state.c
index b34e9f3..fbdb40e 100644
--- a/src/mesa/drivers/dri/i965/brw_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sampler_state.c
@@ -424,10 +424,11 @@ brw_update_sampler_state(struct brw_context *brw,
intel_translate_shadow_compare_func(sampler->CompareFunc);
}
- const unsigned min_lod = U_FIXED(CLAMP(sampler->MinLod, 0, 13), 6);
- const unsigned max_lod = U_FIXED(CLAMP(sampler->MaxLod, 0, 13), 6);
+ const int lod_bits = brw->gen >= 7 ? 8 : 6;
+ const unsigned min_lod = U_FIXED(CLAMP(sampler->MinLod, 0, 13), lod_bits);
+ const unsigned max_lod = U_FIXED(CLAMP(sampler->MaxLod, 0, 13), lod_bits);
const int lod_bias =
- S_FIXED(CLAMP(texUnit->LodBias + sampler->LodBias, -16, 15), 6);
+ S_FIXED(CLAMP(texUnit->LodBias + sampler->LodBias, -16, 15), lod_bits);
const unsigned base_level = U_FIXED(0, 1);
uint32_t border_color_offset;