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| author | Eric Anholt <eric@anholt.net> | 2012-02-09 16:35:49 -0800 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2012-02-14 10:19:04 -0800 |
| commit | 93831a54c7d4e74f353e0029164b1b3262e98806 (patch) | |
| tree | 8914cf94e60d7f11426885f6c8fa831793eefaa1 | |
| parent | a7f46eadea4555ed377928d4e3f89db4a445312e (diff) | |
| download | external_mesa3d-93831a54c7d4e74f353e0029164b1b3262e98806.zip external_mesa3d-93831a54c7d4e74f353e0029164b1b3262e98806.tar.gz external_mesa3d-93831a54c7d4e74f353e0029164b1b3262e98806.tar.bz2 | |
i965/fs: Enable register spilling on gen7 too.
It turns out the same messages work on gen7, we were just being paranoid.
Fixes the penumbra shadows mode of Lightsmark since the register
allocation fix.
NOTE: This is a candidate for release branches.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp index 45f83f3..3a9a415 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp @@ -237,8 +237,6 @@ fs_visitor::assign_regs() if (reg == -1) { fail("no register to spill\n"); - } else if (intel->gen >= 7) { - fail("no spilling support on gen7 yet\n"); } else if (c->dispatch_width == 16) { fail("no spilling support on 16-wide yet\n"); } else { |