i965/ir: Remove backend_reg::reg_offset.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

2 files changed, 2 insertions, 15 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp
index 29435f6..e599235 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -749,8 +749,6 @@ backend_reg::in_range(const backend_reg &r, unsigned n) const
 {
    return (file == r.file &&
            nr == r.nr &&
-           reg_offset >= r.reg_offset &&
-           reg_offset < r.reg_offset + n &&
            offset >= r.offset &&
            offset < r.offset + n * REG_SIZE);
 }
diff --git a/src/mesa/drivers/dri/i965/brw_shader.h b/src/mesa/drivers/dri/i965/brw_shader.h
index 72b94b6..66264b4 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -44,14 +44,14 @@ struct backend_reg : private brw_reg
    const brw_reg &as_brw_reg() const
    {
       assert(file == ARF || file == FIXED_GRF || file == MRF || file == IMM);
-      assert(reg_offset == 0 && offset == 0);
+      assert(offset == 0);
       return static_cast<const brw_reg &>(*this);
    }
 
    brw_reg &as_brw_reg()
    {
       assert(file == ARF || file == FIXED_GRF || file == MRF || file == IMM);
-      assert(reg_offset == 0 && offset == 0);
+      assert(offset == 0);
       return static_cast<brw_reg &>(*this);
    }
 
@@ -64,17 +64,6 @@ struct backend_reg : private brw_reg
    bool is_accumulator() const;
    bool in_range(const backend_reg &r, unsigned n) const;
 
-   /**
-    * Offset within the virtual register.
-    *
-    * In the scalar backend, this is in units of a float per pixel for pre-
-    * register allocation registers (i.e., one register in SIMD8 mode and two
-    * registers in SIMD16 mode).
-    *
-    * For uniforms, this is in units of 1 float.
-    */
-   uint16_t reg_offset;
-
    /** Offset from the start of the (virtual) register in bytes. */
    uint16_t offset;