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authorJordan Justen <jordan.l.justen@intel.com>2016-02-20 01:22:08 -0800
committerJordan Justen <jordan.l.justen@intel.com>2016-03-08 14:27:18 -0800
commita100a57e30010da49c96f84a661cec9c57f9eebe (patch)
tree62ea6932144f326b0df87cf4ef3a70660d54008f
parentd8347f12ead89c5a58f69ce9283a54ac8487159c (diff)
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i965/hsw: Initialize SLM index in state register
For Haswell, we need to initialize the SLM index in the state register. This can be copied out of the CS header dword 0. v2: * Use UW move to avoid changing upper 16-bits of sr0.1 (mattst88) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94081 Fixes: piglit arb_compute_shader/execution/shared-atomics.shader_test Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Cc: "11.2" <mesa-stable@lists.freedesktop.org> Tested-by: Ilia Mirkin <imirkin@alum.mit.edu> (v1) Reviewed-by: Matt Turner <mattst88@gmail.com>
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs.cpp7
-rw-r--r--src/mesa/drivers/dri/i965/brw_reg.h16
2 files changed, 23 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index b5404e1..ff67cf4 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -5470,6 +5470,13 @@ fs_visitor::run_cs()
if (shader_time_index >= 0)
emit_shader_time_begin();
+ if (devinfo->is_haswell && prog_data->total_shared > 0) {
+ /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
+ const fs_builder abld = bld.exec_all().group(1, 0);
+ abld.MOV(retype(suboffset(brw_sr0_reg(), 1), BRW_REGISTER_TYPE_UW),
+ suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW), 1));
+ }
+
emit_nir_code();
if (failed)
diff --git a/src/mesa/drivers/dri/i965/brw_reg.h b/src/mesa/drivers/dri/i965/brw_reg.h
index 74ff67f..4f9b252 100644
--- a/src/mesa/drivers/dri/i965/brw_reg.h
+++ b/src/mesa/drivers/dri/i965/brw_reg.h
@@ -740,6 +740,22 @@ brw_notification_reg(void)
}
static inline struct brw_reg
+brw_sr0_reg(void)
+{
+ return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE,
+ BRW_ARF_STATE,
+ 0,
+ 0,
+ 0,
+ BRW_REGISTER_TYPE_UD,
+ BRW_VERTICAL_STRIDE_8,
+ BRW_WIDTH_8,
+ BRW_HORIZONTAL_STRIDE_1,
+ BRW_SWIZZLE_XYZW,
+ WRITEMASK_XYZW);
+}
+
+static inline struct brw_reg
brw_acc_reg(unsigned width)
{
return brw_vecn_reg(width, BRW_ARCHITECTURE_REGISTER_FILE,