radeon/llvm: Remove auto-generated AMDIL->ISA conversion code

14 files changed, 28 insertions, 280 deletions

diff --git a/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl b/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
deleted file mode 100644
index a77126d..0000000
--- a/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
+++ /dev/null
@@ -1,123 +0,0 @@
-#===-- AMDGPUGenInstrEnums.pl - Script for generating instruction enums ----===#
-#
-#                     The LLVM Compiler Infrastructure
-#
-# This file is distributed under the University of Illinois Open Source
-# License. See LICENSE.TXT for details.
-#
-#===-----------------------------------------------------------------------===#
-#
-# This perl script is used to generate the following files:
-#
-# 1. perl AMDGPUGenInstrEnums.pl td  > AMDGPUInstrEnums.td
-#
-#    This file contains Tablegen constants used for matching hw instructions
-#    from R600 and SI with functionally similar AMDIL instruction.  It aslo
-#    contains definitions of floating point constants like pi (in hex notation)
-#    that are used in some of the shader patterns.
-#
-# 2. perl AMDGPUGenInstrEnums.pl h   > AMDGPUInstrEnums.h
-#
-#    This file contains cpp enums that match the constant values in
-#    AMDGPUInstrEnums.td
-#
-# 3. perl AMDGPUGenInstrEnums.pl inc > AMDGPUInstrEnums.include
-#
-#    This file contains a function called GetRealAMDILOpcode which maps the
-#    constant values defined in AMDGPUInstrEnums.h to the corresponding AMDIL
-#    instructions.
-#===-----------------------------------------------------------------------===#
-
-use warnings;
-use strict;
-
-my @GENERATION_ENUM = qw {
-  R600_CAYMAN
-  R600
-  EG
-  EG_CAYMAN
-  CAYMAN
-  SI
-};
-
-my $FILE_TYPE = $ARGV[0];
-
-open AMDIL, '<', 'AMDILInstructions.td';
-
-my @INST_ENUMS = ('NONE', 'FEQ', 'FGE', 'FLT', 'FNE', 'MOVE_f32', 'MOVE_i32', 'UGT', 'IGE', 'INE', 'UGE', 'IEQ', 'LOG_f32', 'RSQ_f32', 'SIN_f32', 'COS_f32');
-
-while (<AMDIL>) {
-  if ($_ =~ /defm\s+([A-Z_]+)\s+:\s+([A-Za-z0-9]+)</) {
-  } elsif ($_ =~ /def\s+([A-Z_]+)(_[fi]32)/) {
-    push @INST_ENUMS, "$1$2";
-  }
-}
-
-if ($FILE_TYPE eq 'td') {
-
-  print_td_enum('AMDILInst', 'AMDILInstEnums', 'field bits<16>', @INST_ENUMS);
-
-  print_td_enum('AMDGPUGen', 'AMDGPUGenEnums', 'field bits<3>', @GENERATION_ENUM);
-
-  my %constants = (
-    'PI' =>      '0x40490fdb',
-    'TWO_PI' =>     '0x40c90fdb',
-    'TWO_PI_INV' => '0x3e22f983'
-  );
-
-  print "class Constants {\n";
-  foreach (keys(%constants)) {
-    print "int $_ = $constants{$_};\n";
-  }
-  print "}\n";
-  print "def CONST : Constants;\n";
-
-} elsif ($FILE_TYPE eq 'h') {
-
-  print "unsigned GetRealAMDILOpcode(unsigned internalOpcode) const;\n";
-
-  print_h_enum('AMDILTblgenOpcode', @INST_ENUMS);
-
-  print_h_enum('AMDGPUGen', @GENERATION_ENUM);
-
-} elsif ($FILE_TYPE eq 'inc') {
-  print "unsigned AMDGPUInstrInfo::GetRealAMDILOpcode(unsigned internalOpcode) const\n{\n";
-  print "  switch(internalOpcode) {\n";
-  #Start at 1 so we skip NONE
-  for (my $i = 1; $i < scalar(@INST_ENUMS); $i++) {
-    my $inst = $INST_ENUMS[$i];
-    print "  case AMDGPUInstrInfo::$inst: return AMDIL::$inst;\n";
-  }
-  print "  default: abort();\n";
-  print "  }\n}\n";
-}
-
-
-sub print_td_enum {
-  my ($instance, $class, $field, @values) = @_;
-
-  print "class $class {\n";
-
-  for (my $i = 0; $i < scalar(@values); $i++) {
-    print "  $field $values[$i] = $i;\n";
-  }
-  print "}\n";
-
-  print "def $instance : $class;\n";
-}
-
-sub print_h_enum {
-
-  my ($enum, @list) = @_;
-  print "enum $enum {\n";
-
-  for (my $i = 0; $i < scalar(@list); $i++) {
-    print "  $list[$i] = $i";
-    if ($i != $#list) {
-      print ',';
-    }
-    print "\n";
-  }
-  print "};\n";
-}
-
diff --git a/src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp b/src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp
index 2d683c7..3c94c3d 100644
--- a/src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp
@@ -21,52 +21,7 @@
 using namespace llvm;
 
 AMDGPUInstrInfo::AMDGPUInstrInfo(AMDGPUTargetMachine &tm)
-  : AMDILInstrInfo(tm), TM(tm)
-{
-  const AMDILDevice * dev = TM.getSubtarget<AMDILSubtarget>().device();
-  for (unsigned i = 0; i < AMDIL::INSTRUCTION_LIST_END; i++) {
-    const MCInstrDesc & instDesc = get(i);
-    uint32_t instGen = (instDesc.TSFlags >> 40) & 0x7;
-    uint32_t inst = (instDesc.TSFlags >>  48) & 0xffff;
-    if (inst == 0) {
-      continue;
-    }
-    switch (instGen) {
-    case AMDGPUInstrInfo::R600_CAYMAN:
-      if (dev->getGeneration() > AMDILDeviceInfo::HD6XXX) {
-        continue;
-      }
-      break;
-    case AMDGPUInstrInfo::R600:
-      if (dev->getGeneration() != AMDILDeviceInfo::HD4XXX) {
-        continue;
-      }
-      break;
-    case AMDGPUInstrInfo::EG_CAYMAN:
-      if (dev->getGeneration() < AMDILDeviceInfo::HD5XXX
-          || dev->getGeneration() > AMDILDeviceInfo::HD6XXX) {
-        continue;
-      }
-      break;
-    case AMDGPUInstrInfo::CAYMAN:
-      if (dev->getDeviceFlag() != OCL_DEVICE_CAYMAN) {
-        continue;
-      }
-      break;
-    case AMDGPUInstrInfo::SI:
-      if (dev->getGeneration() != AMDILDeviceInfo::HD7XXX) {
-        continue;
-      }
-      break;
-    default:
-      abort();
-      break;
-    }
-
-    unsigned amdilOpcode = GetRealAMDILOpcode(inst);
-    amdilToISA[amdilOpcode] = instDesc.Opcode;
-  }
-}
+  : AMDILInstrInfo(tm), TM(tm) { }
 
 MachineInstr * AMDGPUInstrInfo::convertToISA(MachineInstr & MI, MachineFunction &MF,
     DebugLoc DL) const
@@ -98,14 +53,3 @@ MachineInstr * AMDGPUInstrInfo::convertToISA(MachineInstr & MI, MachineFunction
 
   return newInstr;
 }
-
-unsigned AMDGPUInstrInfo::getISAOpcode(unsigned opcode) const
-{
-  if (amdilToISA.count(opcode) == 0) {
-    return opcode;
-  } else {
-    return amdilToISA.find(opcode)->second;
-  }
-}
-
-#include "AMDGPUInstrEnums.include"
diff --git a/src/gallium/drivers/radeon/AMDGPUInstrInfo.h b/src/gallium/drivers/radeon/AMDGPUInstrInfo.h
index 0f36989..b0d4e8a 100644
--- a/src/gallium/drivers/radeon/AMDGPUInstrInfo.h
+++ b/src/gallium/drivers/radeon/AMDGPUInstrInfo.h
@@ -30,7 +30,6 @@ class MachineInstrBuilder;
 class AMDGPUInstrInfo : public AMDILInstrInfo {
 private:
   AMDGPUTargetMachine & TM;
-  std::map<unsigned, unsigned> amdilToISA;
 
 public:
   explicit AMDGPUInstrInfo(AMDGPUTargetMachine &tm);
@@ -39,14 +38,13 @@ public:
 
   /// getISAOpcode - This function takes an AMDIL opcode as an argument and
   /// returns an equivalent ISA opcode.
-  virtual unsigned getISAOpcode(unsigned AMDILopcode) const;
+  virtual unsigned getISAOpcode(unsigned AMDILopcode) const = 0;
 
   /// convertToISA - Convert the AMDIL MachineInstr to a supported ISA
   /// MachineInstr
   virtual MachineInstr * convertToISA(MachineInstr & MI, MachineFunction &MF,
     DebugLoc DL) const;
 
-  #include "AMDGPUInstrEnums.h.include"
 };
 
 } // End llvm namespace
diff --git a/src/gallium/drivers/radeon/AMDGPUInstructions.td b/src/gallium/drivers/radeon/AMDGPUInstructions.td
index f689356..291081f 100644
--- a/src/gallium/drivers/radeon/AMDGPUInstructions.td
+++ b/src/gallium/drivers/radeon/AMDGPUInstructions.td
@@ -12,8 +12,6 @@
 //
 //===----------------------------------------------------------------------===//
 
-include "AMDGPUInstrEnums.td"
-
 class AMDGPUInst <dag outs, dag ins, string asm, list<dag> pattern> : Instruction {
   field bits<16> AMDILOp = 0;
   field bits<3> Gen = 0;
@@ -34,6 +32,13 @@ class AMDGPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern>
 
 }
 
+class Constants {
+int TWO_PI = 0x40c90fdb;
+int PI = 0x40490fdb;
+int TWO_PI_INV = 0x3e22f983;
+}
+def CONST : Constants;
+
 let isCodeGenOnly = 1 in {
 
   def MASK_WRITE : AMDGPUShaderInst <
diff --git a/src/gallium/drivers/radeon/AMDGPUUtil.cpp b/src/gallium/drivers/radeon/AMDGPUUtil.cpp
index 50e4777..5e36346 100644
--- a/src/gallium/drivers/radeon/AMDGPUUtil.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUUtil.cpp
@@ -44,21 +44,18 @@ bool AMDGPU::isTransOp(unsigned opcode)
   switch(opcode) {
     default: return false;
 
-    case AMDIL::COS_f32:
     case AMDIL::COS_r600:
     case AMDIL::COS_eg:
     case AMDIL::RSQ_f32:
     case AMDIL::MULLIT:
     case AMDIL::MUL_LIT_r600:
     case AMDIL::MUL_LIT_eg:
-    case AMDIL::SIN_f32:
     case AMDIL::EXP_IEEE_r600:
     case AMDIL::EXP_IEEE_eg:
     case AMDIL::LOG_CLAMPED_r600:
     case AMDIL::LOG_IEEE_r600:
     case AMDIL::LOG_CLAMPED_eg:
     case AMDIL::LOG_IEEE_eg:
-    case AMDIL::LOG_f32:
       return true;
   }
 }
diff --git a/src/gallium/drivers/radeon/AMDILInstructions.td b/src/gallium/drivers/radeon/AMDILInstructions.td
index 4907cc5..4d9c163 100644
--- a/src/gallium/drivers/radeon/AMDILInstructions.td
+++ b/src/gallium/drivers/radeon/AMDILInstructions.td
@@ -206,8 +206,6 @@ defm ACOS : UnaryIntrinsicFloatScalar<IL_OP_ACOS, int_AMDIL_acos>;
 defm ATAN : UnaryIntrinsicFloatScalar<IL_OP_ATAN, int_AMDIL_atan>;
 defm ASIN : UnaryIntrinsicFloatScalar<IL_OP_ASIN, int_AMDIL_asin>;
 defm TAN : UnaryIntrinsicFloatScalar<IL_OP_TAN, int_AMDIL_tan>;
-defm SIN : UnaryIntrinsicFloatScalar<IL_OP_SIN, int_AMDIL_sin>;
-defm COS : UnaryIntrinsicFloatScalar<IL_OP_COS, int_AMDIL_cos>;
 defm SQRT : UnaryIntrinsicFloatScalar<IL_OP_SQRT, int_AMDIL_sqrt>;
 defm SQRTVEC : UnaryIntrinsicFloat<IL_OP_SQRT_VEC, int_AMDIL_sqrt_vec>;
 defm COSVEC : UnaryIntrinsicFloat<IL_OP_COS_VEC, int_AMDIL_cos_vec>;
@@ -228,7 +226,6 @@ defm MOD  : BinaryOpMCf32<IL_OP_MOD, frem>;
 let hasZeroOpFlag = 1 in {
   let mayLoad = 0, mayStore=0 in {
 defm LN  : UnaryIntrinsicFloatScalar<IL_OP_LN, int_AMDIL_ln>;
-defm LOG : UnaryIntrinsicFloatScalar<IL_OP_LOG, int_AMDIL_log>;
 defm RSQ : UnaryIntrinsicFloatScalar<IL_OP_RSQ, int_AMDIL_rsq>;
 defm DIV  : BinaryIntrinsicFloat<IL_OP_DIV, int_AMDIL_div>;
   }
diff --git a/src/gallium/drivers/radeon/Makefile b/src/gallium/drivers/radeon/Makefile
index cc40964..3f930cd 100644
--- a/src/gallium/drivers/radeon/Makefile
+++ b/src/gallium/drivers/radeon/Makefile
@@ -38,16 +38,6 @@ endif
 R600RegisterInfo.td: R600GenRegisterInfo.pl
 	$(PERL) $^ > $@
 
-AMDGPUInstrEnums.td: AMDGPUGenInstrEnums.pl
-	$(PERL) $^ td > $@
-
-AMDGPUInstrEnums.h.include: AMDGPUGenInstrEnums.pl
-	$(PERL) $^ h > $@
-
-AMDGPUInstrEnums.include: AMDGPUGenInstrEnums.pl
-	$(PERL) $^ inc > $@
-
-
 AMDILGenRegisterInfo.inc: *.td
 	$(call tablegen, -gen-register-info, AMDIL.td, $@)
 
diff --git a/src/gallium/drivers/radeon/Makefile.sources b/src/gallium/drivers/radeon/Makefile.sources
index fafed6d..099eb02 100644
--- a/src/gallium/drivers/radeon/Makefile.sources
+++ b/src/gallium/drivers/radeon/Makefile.sources
@@ -2,7 +2,6 @@
 GENERATED_SOURCES := \
 	R600Intrinsics.td		\
 	R600RegisterInfo.td		\
-	AMDGPUInstrEnums.td		\
 	SIRegisterInfo.td		\
 	SIRegisterGetHWRegNum.inc		\
 	AMDILGenRegisterInfo.inc	\
@@ -13,9 +12,7 @@ GENERATED_SOURCES := \
 	AMDILGenSubtargetInfo.inc		\
 	AMDILGenEDInfo.inc		\
 	AMDILGenIntrinsics.inc		\
-	AMDILGenCodeEmitter.inc	\
-	AMDGPUInstrEnums.h.include	\
-	AMDGPUInstrEnums.include
+	AMDILGenCodeEmitter.inc
 
 CPP_SOURCES := \
 	AMDIL7XXDevice.cpp		\
diff --git a/src/gallium/drivers/radeon/R600InstrInfo.cpp b/src/gallium/drivers/radeon/R600InstrInfo.cpp
index 42a2257..684c845 100644
--- a/src/gallium/drivers/radeon/R600InstrInfo.cpp
+++ b/src/gallium/drivers/radeon/R600InstrInfo.cpp
@@ -64,7 +64,7 @@ R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
 unsigned R600InstrInfo::getISAOpcode(unsigned opcode) const
 {
   switch (opcode) {
-    default: return AMDGPUInstrInfo::getISAOpcode(opcode);
+    default: return opcode;
     case AMDIL::IEQ:
       return AMDIL::SETE_INT;
     case AMDIL::INE:
diff --git a/src/gallium/drivers/radeon/R600InstrInfo.h b/src/gallium/drivers/radeon/R600InstrInfo.h
index 014eeb0..a499b83 100644
--- a/src/gallium/drivers/radeon/R600InstrInfo.h
+++ b/src/gallium/drivers/radeon/R600InstrInfo.h
@@ -22,13 +22,6 @@
 
 namespace llvm {
 
-  struct InstrGroup {
-    unsigned amdil;
-    unsigned r600;
-    unsigned eg;
-    unsigned cayman;
-  };
-
   class AMDGPUTargetMachine;
   class MachineFunction;
   class MachineInstr;
diff --git a/src/gallium/drivers/radeon/R600Instructions.td b/src/gallium/drivers/radeon/R600Instructions.td
index 7bfd552..3d93d33 100644
--- a/src/gallium/drivers/radeon/R600Instructions.td
+++ b/src/gallium/drivers/radeon/R600Instructions.td
@@ -291,8 +291,6 @@ let Predicates = [isR600toCayman] in {
 /* ------------------------------------------- */
 /* Common Instructions R600, R700, Evergreen, Cayman */
 /* ------------------------------------------- */
-let Gen = AMDGPUGen.R600_CAYMAN  in {
-
 def ADD : R600_2OP <
   0x0, "ADD",
   [(set R600_Reg32:$dst, (fadd R600_Reg32:$src0, R600_Reg32:$src1))]
@@ -330,7 +328,6 @@ def SETE : R600_2OP <
    (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
              COND_EQ))]
 >;
-//let AMDILOp = AMDILInst.FEQ;
 
 def SGT : R600_2OP <
   0x09, "SETGT",
@@ -345,7 +342,6 @@ def SGE : R600_2OP <
    (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
               COND_GE))]
 >;
-//let AMDILOp = AMDILInst.FGE;
 
 def SNE : R600_2OP <
   0xB, "SETNE",
@@ -354,8 +350,6 @@ def SNE : R600_2OP <
     COND_NE))]
 >;
 
-//  let AMDILOp = AMDILInst.FNE;
-
 def FRACT : R600_1OP <
   0x10, "FRACT",
   [(set R600_Reg32:$dst, (AMDGPUfract R600_Reg32:$src))]
@@ -442,8 +436,6 @@ def SETE_INT : R600_2OP <
    (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETEQ))]
 >;
 
-//  let AMDILOp = AMDILInst.IEQ;
-
 def SETGT_INT : R600_2OP <
   0x3B, "SGT_INT",
   [(set (i32 R600_Reg32:$dst),
@@ -455,16 +447,12 @@ def SETGE_INT : R600_2OP <
 	[(set (i32 R600_Reg32:$dst),
    (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGE))]
 >;
-//  let AMDILOp = AMDILInst.IGE;
-
 
 def SETNE_INT : R600_2OP <
   0x3D, "SETNE_INT",
   [(set (i32 R600_Reg32:$dst),
    (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETNE))]
 >;
-//let AMDILOp = AMDILInst.INE;
-
 
 def SETGT_UINT : R600_2OP <
   0x3E, "SETGT_UINT",
@@ -472,14 +460,11 @@ def SETGT_UINT : R600_2OP <
    (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGT))]
 >;
 
-//  let AMDILOp = AMDILInst.UGT;
-
 def SETGE_UINT : R600_2OP <
   0x3F, "SETGE_UINT",
   [(set (i32 R600_Reg32:$dst),
     (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGE))]
 >;
-//  let AMDILOp = AMDILInst.UGE;
 
 def CNDE_INT : R600_3OP <
 	0x1C, "CNDE_INT",
@@ -563,8 +548,6 @@ def TEX_SAMPLE_C_G : R600_TEX <
   []
 >;
 
-} // End Gen R600_CAYMAN
-
 def KILP : Pat <
   (int_AMDGPU_kilp),
   (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO)))
@@ -642,9 +625,8 @@ class LOG_CLAMPED_Common <bits<32> inst> : R600_1OP <
 
 class LOG_IEEE_Common <bits<32> inst> : R600_1OP <
   inst, "LOG_IEEE",
-  []> {
-  let AMDILOp = AMDILInst.LOG_f32;
-}
+  [(set R600_Reg32:$dst, (int_AMDIL_log R600_Reg32:$src))]
+>;
 
 class LSHL_Common <bits<32> inst> : R600_2OP <
   inst, "LSHL $dst, $src0, $src1",
@@ -688,9 +670,8 @@ class RECIP_CLAMPED_Common <bits<32> inst> : R600_1OP <
 
 class RECIP_IEEE_Common <bits<32> inst> : R600_1OP <
   inst, "RECIP_IEEE",
-  [(set R600_Reg32:$dst, (int_AMDGPU_rcp R600_Reg32:$src))]> {
-  let AMDILOp = AMDILInst.RSQ_f32;
-}
+  [(set R600_Reg32:$dst, (int_AMDGPU_rcp R600_Reg32:$src))]
+>;
 
 class RECIP_UINT_Common <bits<32> inst> : R600_1OP <
   inst, "RECIP_INT $dst, $src",
@@ -709,15 +690,13 @@ class RECIPSQRT_IEEE_Common <bits<32> inst> : R600_1OP <
 
 class SIN_Common <bits<32> inst> : R600_1OP <
   inst, "SIN",
-  []>{
-  let AMDILOp = AMDILInst.SIN_f32;
+  [(set R600_Reg32:$dst, (int_AMDIL_sin R600_Reg32:$src))]>{
   let Trig = 1;
 }
 
 class COS_Common <bits<32> inst> : R600_1OP <
   inst, "COS",
-  []> {
-  let AMDILOp = AMDILInst.COS_f32;
+  [(set R600_Reg32:$dst, (int_AMDIL_cos R600_Reg32:$src))]> {
   let Trig = 1;
 }
 
@@ -745,8 +724,6 @@ class TGSI_LIT_Z_Common <InstR600 mul_lit, InstR600 log_clamped, InstR600 exp_ie
 
 let Predicates = [isR600] in {
 
-let Gen = AMDGPUGen.R600 in {
-
   def MUL_LIT_r600 : MUL_LIT_Common<0x0C>;
   def MULADD_r600 : MULADD_Common<0x10>;
   def CNDE_r600 : CNDE_Common<0x18>;
@@ -774,8 +751,6 @@ let Gen = AMDGPUGen.R600 in {
   def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>;
   def RECIP_UINT_r600 : RECIP_UINT_Common <0x77>;
 
-} // End AMDGPUGen.R600
-
   def DIV_r600 : DIV_Common<RECIP_IEEE_r600>;
   def POW_r600 : POW_Common<LOG_IEEE_r600, EXP_IEEE_r600, MUL, GPRF32>;
   def SSG_r600 : SSG_Common<CNDGT_r600, CNDGE_r600>;
@@ -801,8 +776,6 @@ class TRIG_HELPER_r700 <InstR600 trig_inst>: Pat <
 
 let Predicates = [isEG] in {
 
-let Gen = AMDGPUGen.EG in {
-
 def RAT_WRITE_CACHELESS_eg :
     EG_CF_RAT <0x57, 0x2, (outs), (ins R600_TReg32_X:$rw_gpr,
                                    R600_TReg32_X:$index_gpr, i32imm:$rat_id), "">
@@ -891,9 +864,6 @@ def VTX_READ_eg : InstR600ISA < (outs R600_TReg32_X:$dst),
 */
 }
 
-
-
-} // End AMDGPUGen.EG
 /* XXX: Need to convert PTR to rat_id */
 /*
 def : Pat <(store_global (f32 R600_Reg32:$value), node:$ptr),
@@ -923,8 +893,6 @@ class TRIG_eg <InstR600 trig, Intrinsic intr> : Pat<
   (trig (MUL (MOV (LOADCONST_i32 CONST.TWO_PI_INV)), R600_Reg32:$src))
 >;
 
-let Gen = AMDGPUGen.EG_CAYMAN in {
-
   def MULADD_eg : MULADD_Common<0x14>;
   def ASHR_eg : ASHR_Common<0x15>;
   def LSHR_eg : LSHR_Common<0x16>;
@@ -952,8 +920,6 @@ let Gen = AMDGPUGen.EG_CAYMAN in {
   def DOT4_eg : DOT4_Common<0xBE>;
   def CUBE_eg : CUBE_Common<0xC0>;
 
-} // End AMDGPUGen.EG_CAYMAN
-
   def DIV_eg : DIV_Common<RECIP_IEEE_eg>;
   def POW_eg : POW_Common<LOG_IEEE_eg, EXP_IEEE_eg, MUL, GPRF32>;
   def SSG_eg : SSG_Common<CNDGT_eg, CNDGE_eg>;
@@ -966,13 +932,9 @@ let Gen = AMDGPUGen.EG_CAYMAN in {
 
 let Predicates = [isCayman] in {
 
-let Gen = AMDGPUGen.CAYMAN in {
-
   /* XXX: I'm not sure if this opcode is correct. */
   def RECIP_UINT_cm : RECIP_UINT_Common<0x77>;
 
-} // End AMDGPUGen.CAYMAN
-
 } // End isCayman
 
 /* Other Instructions */
diff --git a/src/gallium/drivers/radeon/SIInstrFormats.td b/src/gallium/drivers/radeon/SIInstrFormats.td
index de0d4fa..ac8465c 100644
--- a/src/gallium/drivers/radeon/SIInstrFormats.td
+++ b/src/gallium/drivers/radeon/SIInstrFormats.td
@@ -47,16 +47,10 @@ class VOP1_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
     op, (outs vrc:$dst), (ins arc:$src0), opName, pattern
   >;
 
-multiclass VOP1_32 <bits<8> op, string opName, list<dag> pattern,
-                    bits<16> amdil = AMDILInst.NONE> {
-
-  let AMDILOp = amdil in {
-    def _e32: VOP1_Helper <op, VReg_32, AllReg_32, opName, pattern>;
-  }
-
-  def _e64 : VOP3_32 <
-    {1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
-    opName, []
+multiclass VOP1_32 <bits<8> op, string opName, list<dag> pattern> {
+  def _e32: VOP1_Helper <op, VReg_32, AllReg_32, opName, pattern>;
+  def _e64 : VOP3_32 <{1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
+                      opName, []
   >;
 }
 
@@ -76,16 +70,12 @@ class VOP2_Helper <bits<6> op, RegisterClass vrc, RegisterClass arc,
     op, (outs vrc:$dst), (ins arc:$src0, vrc:$src1), opName, pattern
   >;
 
-multiclass VOP2_32 <bits<6> op, string opName, list<dag> pattern,
-                    bits<16> amdil = AMDILInst.NONE> {
+multiclass VOP2_32 <bits<6> op, string opName, list<dag> pattern> {
 
-  let AMDILOp = amdil in {
-    def _e32 : VOP2_Helper <op, VReg_32, AllReg_32, opName, pattern>;
-  }
+  def _e32 : VOP2_Helper <op, VReg_32, AllReg_32, opName, pattern>;
 
-  def _e64 : VOP3_32 <
-    {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
-    opName, []
+  def _e64 : VOP3_32 <{1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
+                      opName, []
   >;
 }
 
diff --git a/src/gallium/drivers/radeon/SIInstrInfo.cpp b/src/gallium/drivers/radeon/SIInstrInfo.cpp
index 553ac36..d0b39d0 100644
--- a/src/gallium/drivers/radeon/SIInstrInfo.cpp
+++ b/src/gallium/drivers/radeon/SIInstrInfo.cpp
@@ -108,7 +108,8 @@ unsigned SIInstrInfo::getISAOpcode(unsigned AMDILopcode) const
   switch (AMDILopcode) {
   //XXX We need a better way of detecting end of program
   case AMDIL::RETURN: return AMDIL::S_ENDPGM;
-  default: return AMDGPUInstrInfo::getISAOpcode(AMDILopcode);
+  case AMDIL::MOVE_f32: return AMDIL::V_MOV_B32_e32;
+  default: return AMDILopcode;
   }
 }
 
diff --git a/src/gallium/drivers/radeon/SIInstructions.td b/src/gallium/drivers/radeon/SIInstructions.td
index 1818e47..8505df9 100644
--- a/src/gallium/drivers/radeon/SIInstructions.td
+++ b/src/gallium/drivers/radeon/SIInstructions.td
@@ -12,7 +12,6 @@ def isSI : Predicate<"Subtarget.device()"
                             "->getGeneration() == AMDILDeviceInfo::HD7XXX">;
 
 let Predicates = [isSI] in {
-let Gen = AMDGPUGen.SI  in {
 
 def S_MOV_B32 : SOP1_32 <0x00000003, "S_MOV_B32", []>;
 def S_MOV_B64 : SOP1_64 <0x00000004, "S_MOV_B64", []>;
@@ -462,7 +461,7 @@ def IMAGE_SAMPLE : MIMG_Load_Helper <0x00000020, "IMAGE_SAMPLE">;
 //def V_NOP : VOP1_ <0x00000000, "V_NOP", []>;
 
 let neverHasSideEffects = 1 in {
-defm V_MOV_B32 : VOP1_32 <0x00000001, "V_MOV_B32", [], AMDILInst.MOVE_f32>;
+defm V_MOV_B32 : VOP1_32 <0x00000001, "V_MOV_B32", []>;
 }  // End neverHasSideEffects
 defm V_READFIRSTLANE_B32 : VOP1_32 <0x00000002, "V_READFIRSTLANE_B32", []>;
 //defm V_CVT_I32_F64 : VOP1_32 <0x00000003, "V_CVT_I32_F64", []>;
@@ -865,8 +864,6 @@ def VS_LOAD_BUFFER_INDEX : InstSI <
 
 } // end IsCodeGenOnly, isPseudo
 
-} // end Gen = AMDGPUGen.SI
-
 /* int_SI_vs_load_input */
 def : Pat<
   (int_SI_vs_load_input SReg_64:$tlst_sgpr, IMM8bit:$t_offset, IMM12bit:$attr_offset,