r600g: remove is_flush from DSA state

we can just update the state when decompressing, there's no need to add
additional info into the DSA state

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

4 files changed, 16 insertions, 14 deletions

diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c
index d85324b..b6238dc 100644
--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -131,6 +131,13 @@ void r600_blit_uncompress_depth(struct pipe_context *ctx,
 	    rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
 		depth = 0.0f;
 
+	if (rctx->chip_class <= R700 &&
+	    !rctx->db_misc_state.flush_depthstencil_through_cb) {
+		/* Enable decompression in DB_RENDER_CONTROL */
+		rctx->db_misc_state.flush_depthstencil_through_cb = true;
+		r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
+	}
+
 	for (level = 0; level <= texture->resource.b.b.last_level; level++) {
 		unsigned num_layers = u_num_layers(&texture->resource.b.b, level);
 
@@ -161,6 +168,12 @@ void r600_blit_uncompress_depth(struct pipe_context *ctx,
 
 	if (!staging)
 		texture->dirty_db = FALSE;
+
+	if (rctx->chip_class <= R700) {
+		/* Disable decompression in DB_RENDER_CONTROL */
+		rctx->db_misc_state.flush_depthstencil_through_cb = false;
+		r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
+	}
 }
 
 void r600_flush_depth_textures(struct r600_context *rctx)
diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h
index 608cb10..6e08cbf 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -79,7 +79,7 @@ struct r600_surface_sync_cmd {
 struct r600_db_misc_state {
 	struct r600_atom atom;
 	bool occlusion_query_enabled;
-	bool flush_depthstencil_enabled;
+	bool flush_depthstencil_through_cb;
 };
 
 struct r600_cb_misc_state {
@@ -182,7 +182,6 @@ struct r600_pipe_dsa {
 	unsigned			alpha_ref;
 	ubyte				valuemask[2];
 	ubyte				writemask[2];
-	bool				is_flush;
 	unsigned                        sx_alpha_test_control;
 };
 
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index c261797..6c0c0fe 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -1734,7 +1734,7 @@ static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom
 		}
 		db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
 	}
-	if (a->flush_depthstencil_enabled) {
+	if (a->flush_depthstencil_through_cb) {
 		db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(1) |
 				     S_028D0C_STENCIL_COPY_ENABLE(1) |
 				     S_028D0C_COPY_CENTROID(1);
@@ -2457,8 +2457,6 @@ void r600_fetch_shader(struct pipe_context *ctx,
 void *r600_create_db_flush_dsa(struct r600_context *rctx)
 {
 	struct pipe_depth_stencil_alpha_state dsa;
-	struct r600_pipe_state *rstate;
-	struct r600_pipe_dsa *dsa_state;
 	boolean quirk = false;
 
 	if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
@@ -2477,10 +2475,7 @@ void *r600_create_db_flush_dsa(struct r600_context *rctx)
 		dsa.stencil[0].writemask = 0xff;
 	}
 
-	rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
-	dsa_state = (struct r600_pipe_dsa*)rstate;
-	dsa_state->is_flush = true;
-	return rstate;
+	return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
 }
 
 void r600_update_dual_export_state(struct r600_context * rctx)
diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c
index 178ddcc..f3808e6 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -272,11 +272,6 @@ void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
 	ref.writemask[1] = dsa->writemask[1];
 
 	r600_set_stencil_ref(ctx, &ref);
-
-	if (rctx->db_misc_state.flush_depthstencil_enabled != dsa->is_flush) {
-		rctx->db_misc_state.flush_depthstencil_enabled = dsa->is_flush;
-		r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
-	}
 }
 
 void r600_set_max_scissor(struct r600_context *rctx)