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author | Marek Olšák <marek.olsak@amd.com> | 2014-04-20 15:17:23 +0200 |
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committer | Marek Olšák <marek.olsak@amd.com> | 2014-04-25 01:33:12 +0200 |
commit | ef162cf13df96b2c8ab36001b8dab5640cabf05f (patch) | |
tree | d9e60f5bd99d4a13db9af1fc164e908f895372e8 | |
parent | 0967970768c517c8c2f1a969e0a043982b4b1bf7 (diff) | |
download | external_mesa3d-ef162cf13df96b2c8ab36001b8dab5640cabf05f.zip external_mesa3d-ef162cf13df96b2c8ab36001b8dab5640cabf05f.tar.gz external_mesa3d-ef162cf13df96b2c8ab36001b8dab5640cabf05f.tar.bz2 |
r600g: fix for HTILE on R6xx
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r-- | src/gallium/drivers/radeon/r600_texture.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c index 55caece..e30d933 100644 --- a/src/gallium/drivers/radeon/r600_texture.c +++ b/src/gallium/drivers/radeon/r600_texture.c @@ -542,6 +542,12 @@ static unsigned r600_texture_htile_alloc_size(struct r600_common_screen *rscreen return 0; } + /* HW bug on R6xx. */ + if (rscreen->chip_class == R600 && + (rtex->surface.level[0].npix_x > 7680 || + rtex->surface.level[0].npix_y > 7680)) + return 0; + /* this alignment and htile size only apply to linear htile buffer */ sw = align(sw, 16 << 3); sh = align(sh, npipes << 3); |