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| author | Francisco Jerez <currojerez@riseup.net> | 2016-09-01 22:36:15 -0700 |
|---|---|---|
| committer | Francisco Jerez <currojerez@riseup.net> | 2016-09-14 14:50:59 -0700 |
| commit | f33a8f8fcfb6ce3baa8813b32d5eff20506f3df1 (patch) | |
| tree | 356d724a6ed9db82602cf3dde05e6b4a05af4ac0 | |
| parent | 8531f943d9aac13489a02e5a5b4bfa381c465a44 (diff) | |
| download | external_mesa3d-f33a8f8fcfb6ce3baa8813b32d5eff20506f3df1.zip external_mesa3d-f33a8f8fcfb6ce3baa8813b32d5eff20506f3df1.tar.gz external_mesa3d-f33a8f8fcfb6ce3baa8813b32d5eff20506f3df1.tar.bz2 | |
i965/vec4: Don't spill non-GRF-aligned register regions.
A better fix would be to do something along the lines of the FS
back-end spilling code and emit a scratch read before any instruction
that overwrites the register to spill partially due to a non-zero
sub-register offset. In the meantime mark registers used with a
non-zero sub-register offset as no-spill to prevent the spilling code
from miscompiling the program.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp | 5 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 2 |
2 files changed, 5 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp index 947bb49..228e04c 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp @@ -392,7 +392,8 @@ vec4_visitor::evaluate_spill_costs(float *spill_costs, bool *no_spill) */ if (!can_use_scratch_for_source(inst, i, inst->src[i].nr)) { spill_costs[inst->src[i].nr] += loop_scale; - if (inst->src[i].reladdr) + if (inst->src[i].reladdr || + inst->src[i].offset % REG_SIZE != 0) no_spill[inst->src[i].nr] = true; } } @@ -400,7 +401,7 @@ vec4_visitor::evaluate_spill_costs(float *spill_costs, bool *no_spill) if (inst->dst.file == VGRF) { spill_costs[inst->dst.nr] += loop_scale; - if (inst->dst.reladdr) + if (inst->dst.reladdr || inst->dst.offset % REG_SIZE != 0) no_spill[inst->dst.nr] = true; } diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp index a4e4f40..c88d7b6 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp @@ -1481,6 +1481,7 @@ vec4_visitor::emit_scratch_read(bblock_t *block, vec4_instruction *inst, dst_reg temp, src_reg orig_src, int base_offset) { + assert(orig_src.offset % REG_SIZE == 0); int reg_offset = base_offset + orig_src.offset / REG_SIZE; src_reg index = get_scratch_offset(block, inst, orig_src.reladdr, reg_offset); @@ -1498,6 +1499,7 @@ void vec4_visitor::emit_scratch_write(bblock_t *block, vec4_instruction *inst, int base_offset) { + assert(inst->dst.offset % REG_SIZE == 0); int reg_offset = base_offset + inst->dst.offset / REG_SIZE; src_reg index = get_scratch_offset(block, inst, inst->dst.reladdr, reg_offset); |