diff options
| author | Rodrigo Vivi <rodrigo.vivi@gmail.com> | 2013-05-13 17:53:39 -0300 |
|---|---|---|
| committer | Kenneth Graunke <kenneth@whitecape.org> | 2013-06-05 10:44:15 -0700 |
| commit | ce67fb4715e0c2fab01de33da475ef4705622020 (patch) | |
| tree | 35b8c3bcc49bafd0278dbe86e2f717cf99c47849 /include/pci_ids | |
| parent | 3998cfa933dcd9134b75d9f0ae2c9cfcd6f2ee45 (diff) | |
| download | external_mesa3d-ce67fb4715e0c2fab01de33da475ef4705622020.zip external_mesa3d-ce67fb4715e0c2fab01de33da475ef4705622020.tar.gz external_mesa3d-ce67fb4715e0c2fab01de33da475ef4705622020.tar.bz2 | |
i965: Adding more reserved PCI IDs for Haswell.
At DDX commit Chris mentioned the tendency we have of finding out more
PCI IDs only when users report. So Let's add all new reserved Haswell IDs.
NOTE: This is a candidate for stable branches.
Bugzilla: http://bugs.freedesktop.org/show_bug.cgi?id=63701
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'include/pci_ids')
| -rw-r--r-- | include/pci_ids/i965_pci_ids.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h index 3e9765c..808eb4e 100644 --- a/include/pci_ids/i965_pci_ids.h +++ b/include/pci_ids/i965_pci_ids.h @@ -35,6 +35,12 @@ CHIPSET(0x0426, HASWELL_M_GT3, hsw_gt3) CHIPSET(0x040A, HASWELL_S_GT1, hsw_gt1) CHIPSET(0x041A, HASWELL_S_GT2, hsw_gt2) CHIPSET(0x042A, HASWELL_S_GT3, hsw_gt3) +CHIPSET(0x040B, HASWELL_B_GT1, hsw_gt1) +CHIPSET(0x041B, HASWELL_B_GT2, hsw_gt2) +CHIPSET(0x042B, HASWELL_B_GT3, hsw_gt3) +CHIPSET(0x040E, HASWELL_E_GT1, hsw_gt1) +CHIPSET(0x041E, HASWELL_E_GT2, hsw_gt2) +CHIPSET(0x042E, HASWELL_E_GT3, hsw_gt3) CHIPSET(0x0C02, HASWELL_SDV_GT1, hsw_gt1) CHIPSET(0x0C12, HASWELL_SDV_GT2, hsw_gt2) CHIPSET(0x0C22, HASWELL_SDV_GT3, hsw_gt3) @@ -44,6 +50,12 @@ CHIPSET(0x0C26, HASWELL_SDV_M_GT3, hsw_gt3) CHIPSET(0x0C0A, HASWELL_SDV_S_GT1, hsw_gt1) CHIPSET(0x0C1A, HASWELL_SDV_S_GT2, hsw_gt2) CHIPSET(0x0C2A, HASWELL_SDV_S_GT3, hsw_gt3) +CHIPSET(0x0C0B, HASWELL_SDV_B_GT1, hsw_gt1) +CHIPSET(0x0C1B, HASWELL_SDV_B_GT2, hsw_gt2) +CHIPSET(0x0C2B, HASWELL_SDV_B_GT3, hsw_gt3) +CHIPSET(0x0C0E, HASWELL_SDV_E_GT1, hsw_gt1) +CHIPSET(0x0C1E, HASWELL_SDV_E_GT2, hsw_gt2) +CHIPSET(0x0C2E, HASWELL_SDV_E_GT3, hsw_gt3) CHIPSET(0x0A02, HASWELL_ULT_GT1, hsw_gt1) CHIPSET(0x0A12, HASWELL_ULT_GT2, hsw_gt2) CHIPSET(0x0A22, HASWELL_ULT_GT3, hsw_gt3) @@ -53,6 +65,12 @@ CHIPSET(0x0A26, HASWELL_ULT_M_GT3, hsw_gt3) CHIPSET(0x0A0A, HASWELL_ULT_S_GT1, hsw_gt1) CHIPSET(0x0A1A, HASWELL_ULT_S_GT2, hsw_gt2) CHIPSET(0x0A2A, HASWELL_ULT_S_GT3, hsw_gt3) +CHIPSET(0x0A0B, HASWELL_ULT_B_GT1, hsw_gt1) +CHIPSET(0x0A1B, HASWELL_ULT_B_GT2, hsw_gt2) +CHIPSET(0x0A2B, HASWELL_ULT_B_GT3, hsw_gt3) +CHIPSET(0x0A0E, HASWELL_ULT_E_GT1, hsw_gt1) +CHIPSET(0x0A1E, HASWELL_ULT_E_GT2, hsw_gt2) +CHIPSET(0x0A2E, HASWELL_ULT_E_GT3, hsw_gt3) CHIPSET(0x0D02, HASWELL_CRW_GT1, hsw_gt1) CHIPSET(0x0D12, HASWELL_CRW_GT2, hsw_gt2) CHIPSET(0x0D22, HASWELL_CRW_GT3, hsw_gt3) @@ -62,6 +80,12 @@ CHIPSET(0x0D26, HASWELL_CRW_M_GT3, hsw_gt3) CHIPSET(0x0D0A, HASWELL_CRW_S_GT1, hsw_gt1) CHIPSET(0x0D1A, HASWELL_CRW_S_GT2, hsw_gt2) CHIPSET(0x0D2A, HASWELL_CRW_S_GT3, hsw_gt3) +CHIPSET(0x0D0B, HASWELL_CRW_B_GT1, hsw_gt1) +CHIPSET(0x0D1B, HASWELL_CRW_B_GT2, hsw_gt2) +CHIPSET(0x0D2B, HASWELL_CRW_B_GT3, hsw_gt3) +CHIPSET(0x0D0E, HASWELL_CRW_E_GT1, hsw_gt1) +CHIPSET(0x0D1E, HASWELL_CRW_E_GT2, hsw_gt2) +CHIPSET(0x0D2E, HASWELL_CRW_E_GT3, hsw_gt3) CHIPSET(0x0F31, BAYTRAIL_M_1, byt) CHIPSET(0x0F32, BAYTRAIL_M_2, byt) CHIPSET(0x0F33, BAYTRAIL_M_3, byt) |