diff options
| author | Sarah Sharp <sarah.a.sharp@linux.intel.com> | 2015-09-21 14:22:53 -0700 |
|---|---|---|
| committer | Sarah Sharp <sarah.a.sharp@linux.intel.com> | 2016-01-06 15:11:00 -0800 |
| commit | 39c41be50d9474dde4c0dcf23a546d14b212e80a (patch) | |
| tree | 792ddcc7e072bdda2701aec5ff20fc771e50d891 /include | |
| parent | 0819287f562fec991269e03c03e4a622e248930e (diff) | |
| download | external_mesa3d-39c41be50d9474dde4c0dcf23a546d14b212e80a.zip external_mesa3d-39c41be50d9474dde4c0dcf23a546d14b212e80a.tar.gz external_mesa3d-39c41be50d9474dde4c0dcf23a546d14b212e80a.tar.bz2 | |
mesa: Add KBL PCI IDs and platform information.
Add PCI IDs for the Intel Kabylake platforms. The IDs are taken
directly from the Linux kernel patches, which are under review:
http://lists.freedesktop.org/archives/intel-gfx/2015-October/078967.html
http://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=kbl-upstream-v2
The Kabylake PCI IDs taken from the kernel are rearranged to be in order
of GT type, then PCI ID.
Please note that if this patch is backported, the following fixes will
need to be added before this patch:
commit 28ed1e08e8ba98e "i965/skl: Remove early platform support"
commit c1e38ad37042b0e "i965/skl: Use larger URB size where available."
Thanks to Ben for fixing a bug around setting urb.size, and being
patient with my questions about what the various fields mean.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Suggested-by: Ben Widawsky <benjamin.widawsky@intel.com>
Tested-by: Rodrigo Vivi <rodrigo.vivi@intel.com> (KBL-GT2)
Cc: "11.1" <mesa-stable@lists.freedesktop.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/pci_ids/i965_pci_ids.h | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h index 5891ba6..5139e27 100644 --- a/include/pci_ids/i965_pci_ids.h +++ b/include/pci_ids/i965_pci_ids.h @@ -132,6 +132,28 @@ CHIPSET(0x1932, skl_gt4, "Intel(R) Skylake GT4") CHIPSET(0x193A, skl_gt4, "Intel(R) Skylake GT4") CHIPSET(0x193B, skl_gt4, "Intel(R) Skylake GT4") CHIPSET(0x193D, skl_gt4, "Intel(R) Skylake GT4") +CHIPSET(0x5902, kbl_gt1, "Intel(R) Kabylake GT1") +CHIPSET(0x5906, kbl_gt1, "Intel(R) Kabylake GT1") +CHIPSET(0x590A, kbl_gt1, "Intel(R) Kabylake GT1") +CHIPSET(0x590B, kbl_gt1, "Intel(R) Kabylake GT1") +CHIPSET(0x590E, kbl_gt1, "Intel(R) Kabylake GT1") +CHIPSET(0x5913, kbl_gt1_5, "Intel(R) Kabylake GT1.5") +CHIPSET(0x5915, kbl_gt1_5, "Intel(R) Kabylake GT1.5") +CHIPSET(0x5917, kbl_gt1_5, "Intel(R) Kabylake GT1.5") +CHIPSET(0x5912, kbl_gt2, "Intel(R) Kabylake GT2") +CHIPSET(0x5916, kbl_gt2, "Intel(R) Kabylake GT2") +CHIPSET(0x591A, kbl_gt2, "Intel(R) Kabylake GT2") +CHIPSET(0x591B, kbl_gt2, "Intel(R) Kabylake GT2") +CHIPSET(0x591D, kbl_gt2, "Intel(R) Kabylake GT2") +CHIPSET(0x591E, kbl_gt2, "Intel(R) Kabylake GT2") +CHIPSET(0x5921, kbl_gt2, "Intel(R) Kabylake GT2F") +CHIPSET(0x5926, kbl_gt3, "Intel(R) Kabylake GT3") +CHIPSET(0x592A, kbl_gt3, "Intel(R) Kabylake GT3") +CHIPSET(0x592B, kbl_gt3, "Intel(R) Kabylake GT3") +CHIPSET(0x5932, kbl_gt4, "Intel(R) Kabylake GT4") +CHIPSET(0x593A, kbl_gt4, "Intel(R) Kabylake GT4") +CHIPSET(0x593B, kbl_gt4, "Intel(R) Kabylake GT4") +CHIPSET(0x593D, kbl_gt4, "Intel(R) Kabylake GT4") CHIPSET(0x22B0, chv, "Intel(R) HD Graphics (Cherryview)") CHIPSET(0x22B1, chv, "Intel(R) HD Graphics (Cherryview)") CHIPSET(0x22B2, chv, "Intel(R) HD Graphics (Cherryview)") |