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| author | Jason Ekstrand <jason.ekstrand@intel.com> | 2016-05-02 17:28:38 -0700 |
|---|---|---|
| committer | Jason Ekstrand <jason.ekstrand@intel.com> | 2016-05-14 13:34:44 -0700 |
| commit | f47faa431616b36ad0d3811d0bcdd24f8b77cef9 (patch) | |
| tree | 9b7331356c6e1b5825582e7fcfa533052de93ed6 /src/compiler/nir/nir_print.c | |
| parent | 87a41e862b5344da6271d533552a890d59f07a4b (diff) | |
| download | external_mesa3d-f47faa431616b36ad0d3811d0bcdd24f8b77cef9.zip external_mesa3d-f47faa431616b36ad0d3811d0bcdd24f8b77cef9.tar.gz external_mesa3d-f47faa431616b36ad0d3811d0bcdd24f8b77cef9.tar.bz2 | |
nir: Add texture opcodes and source types for multisample compression
Intel hardware does a form of multisample compression that involves an
auxilary surface called the MCS. When an MCS is in use, you have to first
sample from the MCS with a special opcode and then pass the result of that
operation into the next sample instrucion. Normally, we just do this
ourselves in the back-end, but we want to expose that functionality to NIR
so that we can use MCS values directly in NIR-based blorp.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/compiler/nir/nir_print.c')
| -rw-r--r-- | src/compiler/nir/nir_print.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/compiler/nir/nir_print.c b/src/compiler/nir/nir_print.c index a36561e..583f66c 100644 --- a/src/compiler/nir/nir_print.c +++ b/src/compiler/nir/nir_print.c @@ -626,6 +626,9 @@ print_tex_instr(nir_tex_instr *instr, print_state *state) case nir_texop_txf_ms: fprintf(fp, "txf_ms "); break; + case nir_texop_txf_ms_mcs: + fprintf(fp, "txf_ms_mcs "); + break; case nir_texop_txs: fprintf(fp, "txs "); break; @@ -676,6 +679,9 @@ print_tex_instr(nir_tex_instr *instr, print_state *state) case nir_tex_src_ms_index: fprintf(fp, "(ms_index)"); break; + case nir_tex_src_ms_mcs: + fprintf(fp, "(ms_mcs)"); + break; case nir_tex_src_ddx: fprintf(fp, "(ddx)"); break; |