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| author | Rob Clark <robdclark@gmail.com> | 2015-10-17 13:34:24 -0400 |
|---|---|---|
| committer | Rob Clark <robclark@freedesktop.org> | 2016-05-11 12:20:11 -0400 |
| commit | 425dc4c4b3663c619634de9f9f00c7765e7d0320 (patch) | |
| tree | 3053cbc43904815fe895d625e554bcf48235aac8 /src/gallium/auxiliary/tgsi | |
| parent | 4500d17245d0c4bd0b52bf444cf1d90bab932794 (diff) | |
| download | external_mesa3d-425dc4c4b3663c619634de9f9f00c7765e7d0320.zip external_mesa3d-425dc4c4b3663c619634de9f9f00c7765e7d0320.tar.gz external_mesa3d-425dc4c4b3663c619634de9f9f00c7765e7d0320.tar.bz2 | |
gallium: refactor pipe_shader_state to support multiple IR's
The goal is to allow the pipe driver to request something other than
TGSI, but detect whether what is getting is TGSI vs what it requested.
The pipe drivers will always have to support TGSI (and convert that into
whatever it is that they prefer), but in some cases we should be able to
skip the TGSI intermediate step (such as glsl->nir vs glsl->tgsi->nir).
I think pipe_compute_state should get similar treatment. Currently,
afaict, it has one user and one consumer, which has allowed it to be
sloppy wrt. supporting alternative IR's.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Diffstat (limited to 'src/gallium/auxiliary/tgsi')
| -rw-r--r-- | src/gallium/auxiliary/tgsi/tgsi_ureg.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/gallium/auxiliary/tgsi/tgsi_ureg.c b/src/gallium/auxiliary/tgsi/tgsi_ureg.c index 43b8bb1..b67c383 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_ureg.c +++ b/src/gallium/auxiliary/tgsi/tgsi_ureg.c @@ -2019,14 +2019,12 @@ void *ureg_create_shader( struct ureg_program *ureg, { struct pipe_shader_state state; - state.tokens = ureg_finalize(ureg); + pipe_shader_state_from_tgsi(&state, ureg_finalize(ureg)); if(!state.tokens) return NULL; if (so) state.stream_output = *so; - else - memset(&state.stream_output, 0, sizeof(state.stream_output)); switch (ureg->processor) { case PIPE_SHADER_VERTEX: |