ilo: scripted conversion to genhw headers

Hopefully my four hundred line sed script is correct.

12 files changed, 598 insertions, 598 deletions

diff --git a/src/gallium/drivers/ilo/shader/ilo_shader_fs.c b/src/gallium/drivers/ilo/shader/ilo_shader_fs.c
index 817b127..c7a6ff9 100644
--- a/src/gallium/drivers/ilo/shader/ilo_shader_fs.c
+++ b/src/gallium/drivers/ilo/shader/ilo_shader_fs.c
@@ -42,7 +42,7 @@ struct fs_compile_context {
    struct toy_compiler tc;
    struct toy_tgsi tgsi;
 
-   enum brw_message_target const_cache;
+   int const_cache;
    int dispatch_mode;
 
    struct {
@@ -218,7 +218,7 @@ fetch_attr(struct fs_compile_context *fcc, struct toy_dst dst, int slot)
       uv = tsrc(TOY_FILE_GRF, interp, 0);
 
       for (ch = 0; ch < 4; ch++) {
-         tc_add2(tc, BRW_OPCODE_PLN, real_dst[ch],
+         tc_add2(tc, GEN6_OPCODE_PLN, real_dst[ch],
                tsrc_rect(attr[ch], TOY_RECT_010), uv);
       }
    }
@@ -273,15 +273,15 @@ fs_lower_opcode_tgsi_indirect_const(struct fs_compile_context *fcc,
 
    /* set offset */
    inst = tc_MOV(tc, offset, real_src[0]);
-   inst->mask_ctrl = BRW_MASK_DISABLE;
+   inst->mask_ctrl = GEN6_MASKCTRL_NOMASK;
 
    switch (inst->exec_size) {
-   case BRW_EXECUTE_8:
-      simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
+   case GEN6_EXECSIZE_8:
+      simd_mode = GEN6_MSG_SAMPLER_SIMD8;
       param_size = 1;
       break;
-   case BRW_EXECUTE_16:
-      simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
+   case GEN6_EXECSIZE_16:
+      simd_mode = GEN6_MSG_SAMPLER_SIMD16;
       param_size = 2;
       break;
    default:
@@ -293,13 +293,13 @@ fs_lower_opcode_tgsi_indirect_const(struct fs_compile_context *fcc,
 
    desc = tsrc_imm_mdesc_sampler(tc, param_size, param_size * 4, false,
          simd_mode,
-         GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
+         GEN6_MSG_SAMPLER_LD,
          0,
          ILO_WM_CONST_SURFACE(dim));
 
    tmp = tdst(TOY_FILE_VRF, tc_alloc_vrf(tc, param_size * 4), 0);
-   inst = tc_SEND(tc, tmp, tsrc_from(offset), desc, BRW_SFID_SAMPLER);
-   inst->mask_ctrl = BRW_MASK_DISABLE;
+   inst = tc_SEND(tc, tmp, tsrc_from(offset), desc, GEN6_SFID_SAMPLER);
+   inst->mask_ctrl = GEN6_MASKCTRL_NOMASK;
 
    tdst_transpose(dst, real_dst);
    for (i = 0; i < 4; i++) {
@@ -358,16 +358,16 @@ fs_lower_opcode_tgsi_const_gen6(struct fs_compile_context *fcc,
 
    /* set message header */
    inst = tc_MOV(tc, header, r0);
-   inst->mask_ctrl = BRW_MASK_DISABLE;
+   inst->mask_ctrl = GEN6_MASKCTRL_NOMASK;
 
    /* set global offset */
    inst = tc_MOV(tc, global_offset, idx);
-   inst->mask_ctrl = BRW_MASK_DISABLE;
-   inst->exec_size = BRW_EXECUTE_1;
+   inst->mask_ctrl = GEN6_MASKCTRL_NOMASK;
+   inst->exec_size = GEN6_EXECSIZE_1;
    inst->src[0].rect = TOY_RECT_010;
 
-   msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ;
-   msg_ctrl = BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW << 8;
+   msg_type = GEN6_MSG_DP_OWORD_BLOCK_READ;
+   msg_ctrl = GEN6_MSG_DP_OWORD_BLOCK_SIZE_1_LO;
    msg_len = 1;
 
    desc = tsrc_imm_mdesc_data_port(tc, false, msg_len, 1, true, false,
@@ -411,19 +411,19 @@ fs_lower_opcode_tgsi_const_gen7(struct fs_compile_context *fcc,
 
    /* set offset */
    inst = tc_MOV(tc, offset, tsrc_rect(idx, TOY_RECT_010));
-   inst->exec_size = BRW_EXECUTE_8;
-   inst->mask_ctrl = BRW_MASK_DISABLE;
+   inst->exec_size = GEN6_EXECSIZE_8;
+   inst->mask_ctrl = GEN6_MASKCTRL_NOMASK;
 
    desc = tsrc_imm_mdesc_sampler(tc, 1, 1, false,
-         BRW_SAMPLER_SIMD_MODE_SIMD4X2,
-         GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
+         GEN6_MSG_SAMPLER_SIMD4X2,
+         GEN6_MSG_SAMPLER_LD,
          0,
          ILO_WM_CONST_SURFACE(dim));
 
    tmp = tc_alloc_tmp(tc);
-   inst = tc_SEND(tc, tmp, tsrc_from(offset), desc, BRW_SFID_SAMPLER);
-   inst->exec_size = BRW_EXECUTE_8;
-   inst->mask_ctrl = BRW_MASK_DISABLE;
+   inst = tc_SEND(tc, tmp, tsrc_from(offset), desc, GEN6_SFID_SAMPLER);
+   inst->exec_size = GEN6_EXECSIZE_8;
+   inst->mask_ctrl = GEN6_MASKCTRL_NOMASK;
 
    tdst_transpose(dst, real_dst);
    for (i = 0; i < 4; i++) {
@@ -579,25 +579,25 @@ fs_add_sampler_params_gen6(struct toy_compiler *tc, int msg_type,
 
 #define SAMPLER_PARAM(p) (tdst(TOY_FILE_MRF, base_mrf + (p) * param_size, 0))
    switch (msg_type) {
-   case GEN5_SAMPLER_MESSAGE_SAMPLE:
+   case GEN6_MSG_SAMPLER_SAMPLE:
       for (i = 0; i < num_coords; i++)
          tc_MOV(tc, SAMPLER_PARAM(i), coords[i]);
       num_params = num_coords;
       break;
-   case GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS:
-   case GEN5_SAMPLER_MESSAGE_SAMPLE_LOD:
+   case GEN6_MSG_SAMPLER_SAMPLE_B:
+   case GEN6_MSG_SAMPLER_SAMPLE_L:
       for (i = 0; i < num_coords; i++)
          tc_MOV(tc, SAMPLER_PARAM(i), coords[i]);
       tc_MOV(tc, SAMPLER_PARAM(4), bias_or_lod);
       num_params = 5;
       break;
-   case GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE:
+   case GEN6_MSG_SAMPLER_SAMPLE_C:
       for (i = 0; i < num_coords; i++)
          tc_MOV(tc, SAMPLER_PARAM(i), coords[i]);
       tc_MOV(tc, SAMPLER_PARAM(4), ref_or_si);
       num_params = 5;
       break;
-   case GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS:
+   case GEN6_MSG_SAMPLER_SAMPLE_D:
       for (i = 0; i < num_coords; i++)
          tc_MOV(tc, SAMPLER_PARAM(i), coords[i]);
       for (i = 0; i < num_derivs; i++) {
@@ -606,15 +606,15 @@ fs_add_sampler_params_gen6(struct toy_compiler *tc, int msg_type,
       }
       num_params = 4 + num_derivs * 2;
       break;
-   case GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE:
-   case GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE:
+   case GEN6_MSG_SAMPLER_SAMPLE_B_C:
+   case GEN6_MSG_SAMPLER_SAMPLE_L_C:
       for (i = 0; i < num_coords; i++)
          tc_MOV(tc, SAMPLER_PARAM(i), coords[i]);
       tc_MOV(tc, SAMPLER_PARAM(4), ref_or_si);
       tc_MOV(tc, SAMPLER_PARAM(5), bias_or_lod);
       num_params = 6;
       break;
-   case GEN5_SAMPLER_MESSAGE_SAMPLE_LD:
+   case GEN6_MSG_SAMPLER_LD:
       assert(num_coords <= 3);
 
       for (i = 0; i < num_coords; i++)
@@ -623,7 +623,7 @@ fs_add_sampler_params_gen6(struct toy_compiler *tc, int msg_type,
       tc_MOV(tc, tdst_d(SAMPLER_PARAM(4)), ref_or_si);
       num_params = 5;
       break;
-   case GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO:
+   case GEN6_MSG_SAMPLER_RESINFO:
       tc_MOV(tc, tdst_d(SAMPLER_PARAM(0)), bias_or_lod);
       num_params = 1;
       break;
@@ -652,25 +652,25 @@ fs_add_sampler_params_gen7(struct toy_compiler *tc, int msg_type,
 
 #define SAMPLER_PARAM(p) (tdst(TOY_FILE_MRF, base_mrf + (p) * param_size, 0))
    switch (msg_type) {
-   case GEN5_SAMPLER_MESSAGE_SAMPLE:
+   case GEN6_MSG_SAMPLER_SAMPLE:
       for (i = 0; i < num_coords; i++)
          tc_MOV(tc, SAMPLER_PARAM(i), coords[i]);
       num_params = num_coords;
       break;
-   case GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS:
-   case GEN5_SAMPLER_MESSAGE_SAMPLE_LOD:
+   case GEN6_MSG_SAMPLER_SAMPLE_B:
+   case GEN6_MSG_SAMPLER_SAMPLE_L:
       tc_MOV(tc, SAMPLER_PARAM(0), bias_or_lod);
       for (i = 0; i < num_coords; i++)
          tc_MOV(tc, SAMPLER_PARAM(1 + i), coords[i]);
       num_params = 1 + num_coords;
       break;
-   case GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE:
+   case GEN6_MSG_SAMPLER_SAMPLE_C:
       tc_MOV(tc, SAMPLER_PARAM(0), ref_or_si);
       for (i = 0; i < num_coords; i++)
          tc_MOV(tc, SAMPLER_PARAM(1 + i), coords[i]);
       num_params = 1 + num_coords;
       break;
-   case GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS:
+   case GEN6_MSG_SAMPLER_SAMPLE_D:
       for (i = 0; i < num_coords; i++) {
          tc_MOV(tc, SAMPLER_PARAM(i * 3), coords[i]);
          if (i < num_derivs) {
@@ -680,15 +680,15 @@ fs_add_sampler_params_gen7(struct toy_compiler *tc, int msg_type,
       }
       num_params = num_coords * 3 - ((num_coords > num_derivs) ? 2 : 0);
       break;
-   case GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE:
-   case GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE:
+   case GEN6_MSG_SAMPLER_SAMPLE_B_C:
+   case GEN6_MSG_SAMPLER_SAMPLE_L_C:
       tc_MOV(tc, SAMPLER_PARAM(0), ref_or_si);
       tc_MOV(tc, SAMPLER_PARAM(1), bias_or_lod);
       for (i = 0; i < num_coords; i++)
          tc_MOV(tc, SAMPLER_PARAM(2 + i), coords[i]);
       num_params = 2 + num_coords;
       break;
-   case GEN5_SAMPLER_MESSAGE_SAMPLE_LD:
+   case GEN6_MSG_SAMPLER_LD:
       assert(num_coords >= 1 && num_coords <= 3);
 
       tc_MOV(tc, tdst_d(SAMPLER_PARAM(0)), coords[0]);
@@ -697,7 +697,7 @@ fs_add_sampler_params_gen7(struct toy_compiler *tc, int msg_type,
          tc_MOV(tc, tdst_d(SAMPLER_PARAM(1 + i)), coords[i]);
       num_params = 1 + num_coords;
       break;
-   case GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO:
+   case GEN6_MSG_SAMPLER_RESINFO:
       tc_MOV(tc, tdst_d(SAMPLER_PARAM(0)), bias_or_lod);
       num_params = 1;
       break;
@@ -725,12 +725,12 @@ fs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst,
    int sampler_src, param_size, i;
 
    switch (inst->exec_size) {
-   case BRW_EXECUTE_8:
-      simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
+   case GEN6_EXECSIZE_8:
+      simd_mode = GEN6_MSG_SAMPLER_SIMD8;
       param_size = 1;
       break;
-   case BRW_EXECUTE_16:
-      simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
+   case GEN6_EXECSIZE_16:
+      simd_mode = GEN6_MSG_SAMPLER_SIMD16;
       param_size = 2;
       break;
    default:
@@ -787,25 +787,25 @@ fs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst,
       if (ref_pos >= 0) {
          assert(ref_pos < 4);
 
-         msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
+         msg_type = GEN6_MSG_SAMPLER_SAMPLE_C;
          ref_or_si = coords[ref_pos];
       }
       else {
-         msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
+         msg_type = GEN6_MSG_SAMPLER_SAMPLE;
       }
       break;
    case TOY_OPCODE_TGSI_TXD:
       if (ref_pos >= 0) {
          assert(ref_pos < 4);
 
-         msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
+         msg_type = GEN7_MSG_SAMPLER_SAMPLE_D_C;
          ref_or_si = coords[ref_pos];
 
          if (tc->dev->gen < ILO_GEN(7.5))
             tc_fail(tc, "TXD with shadow sampler not supported");
       }
       else {
-         msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
+         msg_type = GEN6_MSG_SAMPLER_SAMPLE_D;
       }
 
       tsrc_transpose(inst->src[1], ddx);
@@ -817,11 +817,11 @@ fs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst,
       if (ref_pos >= 0) {
          assert(ref_pos < 3);
 
-         msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
+         msg_type = GEN6_MSG_SAMPLER_SAMPLE_C;
          ref_or_si = coords[ref_pos];
       }
       else {
-         msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
+         msg_type = GEN6_MSG_SAMPLER_SAMPLE;
       }
 
       /* project the coordinates */
@@ -846,11 +846,11 @@ fs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst,
       if (ref_pos >= 0) {
          assert(ref_pos < 3);
 
-         msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
+         msg_type = GEN6_MSG_SAMPLER_SAMPLE_B_C;
          ref_or_si = coords[ref_pos];
       }
       else {
-         msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
+         msg_type = GEN6_MSG_SAMPLER_SAMPLE_B;
       }
 
       bias_or_lod = coords[3];
@@ -859,17 +859,17 @@ fs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst,
       if (ref_pos >= 0) {
          assert(ref_pos < 3);
 
-         msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
+         msg_type = GEN6_MSG_SAMPLER_SAMPLE_L_C;
          ref_or_si = coords[ref_pos];
       }
       else {
-         msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
+         msg_type = GEN6_MSG_SAMPLER_SAMPLE_L;
       }
 
       bias_or_lod = coords[3];
       break;
    case TOY_OPCODE_TGSI_TXF:
-      msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
+      msg_type = GEN6_MSG_SAMPLER_LD;
 
       switch (inst->tex.target) {
       case TGSI_TEXTURE_2D_MSAA:
@@ -901,12 +901,12 @@ fs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst,
       sampler_src = 1;
       break;
    case TOY_OPCODE_TGSI_TXQ:
-      msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
+      msg_type = GEN6_MSG_SAMPLER_RESINFO;
       num_coords = 0;
       bias_or_lod = coords[0];
       break;
    case TOY_OPCODE_TGSI_TXQ_LZ:
-      msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
+      msg_type = GEN6_MSG_SAMPLER_RESINFO;
       num_coords = 0;
       sampler_src = 0;
       break;
@@ -914,7 +914,7 @@ fs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst,
       if (ref_pos >= 0) {
          assert(ref_pos < 5);
 
-         msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
+         msg_type = GEN6_MSG_SAMPLER_SAMPLE_C;
 
          if (ref_pos >= 4) {
             struct toy_src src1[4];
@@ -926,7 +926,7 @@ fs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst,
          }
       }
       else {
-         msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
+         msg_type = GEN6_MSG_SAMPLER_SAMPLE;
       }
 
       sampler_src = 2;
@@ -935,11 +935,11 @@ fs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst,
       if (ref_pos >= 0) {
          assert(ref_pos < 4);
 
-         msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
+         msg_type = GEN6_MSG_SAMPLER_SAMPLE_B_C;
          ref_or_si = coords[ref_pos];
       }
       else {
-         msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
+         msg_type = GEN6_MSG_SAMPLER_SAMPLE_B;
       }
 
       {
@@ -954,11 +954,11 @@ fs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst,
       if (ref_pos >= 0) {
          assert(ref_pos < 4);
 
-         msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
+         msg_type = GEN6_MSG_SAMPLER_SAMPLE_L_C;
          ref_or_si = coords[ref_pos];
       }
       else {
-         msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
+         msg_type = GEN6_MSG_SAMPLER_SAMPLE_L;
       }
 
       {
@@ -998,9 +998,9 @@ fs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst,
          tc_alloc_tmp4(tc, tmp);
 
          tc_SEL(tc, tmp[3], tsrc_absolute(coords[0]),
-               tsrc_absolute(coords[1]), BRW_CONDITIONAL_GE);
+               tsrc_absolute(coords[1]), GEN6_COND_GE);
          tc_SEL(tc, tmp[3], tsrc_from(tmp[3]),
-               tsrc_absolute(coords[2]), BRW_CONDITIONAL_GE);
+               tsrc_absolute(coords[2]), GEN6_COND_GE);
          tc_INV(tc, tmp[3], tsrc_from(tmp[3]));
 
          for (i = 0; i < 3; i++) {
@@ -1044,8 +1044,8 @@ fs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst,
          min = tsrc_imm_f(0.0f);
          max = tsrc_imm_f(2048.0f);
 
-         tc_SEL(tc, tmp, coords[i], min, BRW_CONDITIONAL_G);
-         tc_SEL(tc, tmp, tsrc_from(tmp), max, BRW_CONDITIONAL_L);
+         tc_SEL(tc, tmp, coords[i], min, GEN6_COND_G);
+         tc_SEL(tc, tmp, tsrc_from(tmp), max, GEN6_COND_L);
 
          coords[i] = tsrc_from(tmp);
       }
@@ -1117,7 +1117,7 @@ fs_lower_opcode_tgsi_sampling(struct fs_compile_context *fcc,
       break;
    }
 
-   toy_compiler_lower_to_send(tc, inst, false, BRW_SFID_SAMPLER);
+   toy_compiler_lower_to_send(tc, inst, false, GEN6_SFID_SAMPLER);
    inst->src[0] = tsrc(TOY_FILE_MRF, fcc->first_free_mrf, 0);
    inst->src[1] = desc;
    for (i = 2; i < Elements(inst->src); i++)
@@ -1188,7 +1188,7 @@ fs_lower_opcode_derivative(struct toy_compiler *tc, struct toy_inst *inst)
     *
     *   dst = src.zzww - src.xxyy
     *
-    * But since we are in BRW_ALIGN_1, swizzling does not work and we have to
+    * But since we are in GEN6_ALIGN_1, swizzling does not work and we have to
     * play with the region parameters.
     */
    if (inst->opcode == TOY_OPCODE_DDX) {
@@ -1221,7 +1221,7 @@ fs_lower_opcode_fb_write(struct toy_compiler *tc, struct toy_inst *inst)
 {
    /* fs_write_fb() has set up the message registers */
    toy_compiler_lower_to_send(tc, inst, true,
-         GEN6_SFID_DATAPORT_RENDER_CACHE);
+         GEN6_SFID_DP_RC);
 }
 
 static void
@@ -1235,24 +1235,24 @@ fs_lower_opcode_kil(struct toy_compiler *tc, struct toy_inst *inst)
    pixel_mask_dst = tdst_uw(tdst(TOY_FILE_GRF, 1, 7 * 4));
    pixel_mask = tsrc_rect(tsrc_from(pixel_mask_dst), TOY_RECT_010);
 
-   f0 = tsrc_rect(tsrc_uw(tsrc(TOY_FILE_ARF, BRW_ARF_FLAG, 0)), TOY_RECT_010);
+   f0 = tsrc_rect(tsrc_uw(tsrc(TOY_FILE_ARF, GEN6_ARF_F0, 0)), TOY_RECT_010);
 
    /* KILL or KILL_IF */
    if (tsrc_is_null(inst->src[0])) {
       struct toy_src dummy = tsrc_uw(tsrc(TOY_FILE_GRF, 0, 0));
-      struct toy_dst f0_dst = tdst_uw(tdst(TOY_FILE_ARF, BRW_ARF_FLAG, 0));
+      struct toy_dst f0_dst = tdst_uw(tdst(TOY_FILE_ARF, GEN6_ARF_F0, 0));
 
       /* create a mask that masks out all pixels */
       tmp = tc_MOV(tc, f0_dst, tsrc_rect(tsrc_imm_uw(0xffff), TOY_RECT_010));
-      tmp->exec_size = BRW_EXECUTE_1;
-      tmp->mask_ctrl = BRW_MASK_DISABLE;
+      tmp->exec_size = GEN6_EXECSIZE_1;
+      tmp->mask_ctrl = GEN6_MASKCTRL_NOMASK;
 
-      tc_CMP(tc, tdst_null(), dummy, dummy, BRW_CONDITIONAL_NEQ);
+      tc_CMP(tc, tdst_null(), dummy, dummy, GEN6_COND_NZ);
 
       /* swapping the two src operands breaks glBitmap()!? */
       tmp = tc_AND(tc, pixel_mask_dst, f0, pixel_mask);
-      tmp->exec_size = BRW_EXECUTE_1;
-      tmp->mask_ctrl = BRW_MASK_DISABLE;
+      tmp->exec_size = GEN6_EXECSIZE_1;
+      tmp->mask_ctrl = GEN6_MASKCTRL_NOMASK;
    }
    else {
       struct toy_src src[4];
@@ -1262,12 +1262,12 @@ fs_lower_opcode_kil(struct toy_compiler *tc, struct toy_inst *inst)
       /* mask out killed pixels */
       for (i = 0; i < 4; i++) {
          tc_CMP(tc, tdst_null(), src[i], tsrc_imm_f(0.0f),
-               BRW_CONDITIONAL_GE);
+               GEN6_COND_GE);
 
          /* swapping the two src operands breaks glBitmap()!? */
          tmp = tc_AND(tc, pixel_mask_dst, f0, pixel_mask);
-         tmp->exec_size = BRW_EXECUTE_1;
-         tmp->mask_ctrl = BRW_MASK_DISABLE;
+         tmp->exec_size = GEN6_EXECSIZE_1;
+         tmp->mask_ctrl = GEN6_MASKCTRL_NOMASK;
       }
    }
 
@@ -1471,13 +1471,13 @@ fs_write_fb(struct fs_compile_context *fcc)
       struct toy_inst *inst;
 
       inst = tc_MOV(tc, header, r0);
-      inst->mask_ctrl = BRW_MASK_DISABLE;
+      inst->mask_ctrl = GEN6_MASKCTRL_NOMASK;
       base_mrf += fcc->num_grf_per_vrf;
 
       /* this is a two-register header */
-      if (fcc->dispatch_mode == GEN6_WM_8_DISPATCH_ENABLE) {
+      if (fcc->dispatch_mode == GEN6_WM_DW5_8_PIXEL_DISPATCH) {
          inst = tc_MOV(tc, tdst_offset(header, 1, 0), tsrc_offset(r0, 1, 0));
-         inst->mask_ctrl = BRW_MASK_DISABLE;
+         inst->mask_ctrl = GEN6_MASKCTRL_NOMASK;
          base_mrf += fcc->num_grf_per_vrf;
       }
 
@@ -1531,8 +1531,8 @@ fs_write_fb(struct fs_compile_context *fcc)
          struct toy_inst *inst;
 
          inst = tc_MOV(tc, tdst_offset(header, 0, 2), tsrc_imm_ud(cbuf));
-         inst->mask_ctrl = BRW_MASK_DISABLE;
-         inst->exec_size = BRW_EXECUTE_1;
+         inst->mask_ctrl = GEN6_MASKCTRL_NOMASK;
+         inst->exec_size = GEN6_EXECSIZE_1;
          inst->src[0].rect = TOY_RECT_010;
       }
 
@@ -1558,9 +1558,9 @@ fs_write_fb(struct fs_compile_context *fcc)
          mrf += fcc->num_grf_per_vrf;
       }
 
-      msg_type = (fcc->dispatch_mode == GEN6_WM_16_DISPATCH_ENABLE) ?
-         BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE :
-         BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
+      msg_type = (fcc->dispatch_mode == GEN6_WM_DW5_16_PIXEL_DISPATCH) ?
+         GEN6_MSG_DP_RT_MODE_SIMD16 >> 8 :
+         GEN6_MSG_DP_RT_MODE_SIMD8_LO >> 8;
 
       ctrl = (cbuf == num_cbufs - 1) << 12 |
              msg_type << 8;
@@ -1568,7 +1568,7 @@ fs_write_fb(struct fs_compile_context *fcc)
       desc = tsrc_imm_mdesc_data_port(tc, cbuf == num_cbufs - 1,
             mrf - fcc->first_free_mrf, 0,
             header_present, false,
-            GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE,
+            GEN6_MSG_DP_RT_WRITE,
             ctrl, ILO_WM_DRAW_SURFACE(cbuf));
 
       tc_add2(tc, TOY_OPCODE_FB_WRITE, tdst_null(),
@@ -1628,11 +1628,11 @@ fs_setup_shader_in(struct ilo_shader *sh, const struct toy_tgsi *tgsi,
 
          if (tgsi->inputs[i].centroid) {
             sh->in.barycentric_interpolation_mode |=
-               1 << BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC;
+               GEN6_INTERP_NONPERSPECTIVE_CENTROID;
          }
          else {
             sh->in.barycentric_interpolation_mode |=
-               1 << BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC;
+               GEN6_INTERP_NONPERSPECTIVE_PIXEL;
          }
          break;
       case TGSI_INTERPOLATE_COLOR:
@@ -1644,11 +1644,11 @@ fs_setup_shader_in(struct ilo_shader *sh, const struct toy_tgsi *tgsi,
       case TGSI_INTERPOLATE_PERSPECTIVE:
          if (tgsi->inputs[i].centroid) {
             sh->in.barycentric_interpolation_mode |=
-               1 << BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC;
+               GEN6_INTERP_PERSPECTIVE_CENTROID;
          }
          else {
             sh->in.barycentric_interpolation_mode |=
-               1 << BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC;
+               GEN6_INTERP_PERSPECTIVE_PIXEL;
          }
          break;
       default:
@@ -1669,40 +1669,40 @@ fs_setup_payloads(struct fs_compile_context *fcc)
    grf++;
 
    /* r1-r2: coordinates and etc. */
-   grf += (fcc->dispatch_mode == GEN6_WM_32_DISPATCH_ENABLE) ? 2 : 1;
+   grf += (fcc->dispatch_mode == GEN6_WM_DW5_32_PIXEL_DISPATCH) ? 2 : 1;
 
    for (i = 0; i < Elements(fcc->payloads); i++) {
       const int reg_scale =
-         (fcc->dispatch_mode == GEN6_WM_8_DISPATCH_ENABLE) ? 1 : 2;
+         (fcc->dispatch_mode == GEN6_WM_DW5_8_PIXEL_DISPATCH) ? 1 : 2;
 
       /* r3-r26 or r32-r55: barycentric interpolation parameters */
       if (sh->in.barycentric_interpolation_mode &
-            (1 << BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC)) {
+            (GEN6_INTERP_PERSPECTIVE_PIXEL)) {
          fcc->payloads[i].interp_perspective_pixel = grf;
          grf += 2 * reg_scale;
       }
       if (sh->in.barycentric_interpolation_mode &
-            (1 << BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC)) {
+            (GEN6_INTERP_PERSPECTIVE_CENTROID)) {
          fcc->payloads[i].interp_perspective_centroid = grf;
          grf += 2 * reg_scale;
       }
       if (sh->in.barycentric_interpolation_mode &
-            (1 << BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC)) {
+            (GEN6_INTERP_PERSPECTIVE_SAMPLE)) {
          fcc->payloads[i].interp_perspective_sample = grf;
          grf += 2 * reg_scale;
       }
       if (sh->in.barycentric_interpolation_mode &
-            (1 << BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC)) {
+            (GEN6_INTERP_NONPERSPECTIVE_PIXEL)) {
          fcc->payloads[i].interp_nonperspective_pixel = grf;
          grf += 2 * reg_scale;
       }
       if (sh->in.barycentric_interpolation_mode &
-            (1 << BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC)) {
+            (GEN6_INTERP_NONPERSPECTIVE_CENTROID)) {
          fcc->payloads[i].interp_nonperspective_centroid = grf;
          grf += 2 * reg_scale;
       }
       if (sh->in.barycentric_interpolation_mode &
-            (1 << BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC)) {
+            (GEN6_INTERP_NONPERSPECTIVE_SAMPLE)) {
          fcc->payloads[i].interp_nonperspective_sample = grf;
          grf += 2 * reg_scale;
       }
@@ -1725,7 +1725,7 @@ fs_setup_payloads(struct fs_compile_context *fcc)
          grf++;
       }
 
-      if (fcc->dispatch_mode != GEN6_WM_32_DISPATCH_ENABLE)
+      if (fcc->dispatch_mode != GEN6_WM_DW5_32_PIXEL_DISPATCH)
          break;
    }
 
@@ -1784,16 +1784,16 @@ fs_setup(struct fs_compile_context *fcc,
 
    toy_compiler_init(&fcc->tc, state->info.dev);
 
-   fcc->dispatch_mode = GEN6_WM_8_DISPATCH_ENABLE;
+   fcc->dispatch_mode = GEN6_WM_DW5_8_PIXEL_DISPATCH;
 
-   fcc->tc.templ.access_mode = BRW_ALIGN_1;
-   if (fcc->dispatch_mode == GEN6_WM_16_DISPATCH_ENABLE) {
-      fcc->tc.templ.qtr_ctrl = GEN6_COMPRESSION_1H;
-      fcc->tc.templ.exec_size = BRW_EXECUTE_16;
+   fcc->tc.templ.access_mode = GEN6_ALIGN_1;
+   if (fcc->dispatch_mode == GEN6_WM_DW5_16_PIXEL_DISPATCH) {
+      fcc->tc.templ.qtr_ctrl = GEN6_QTRCTRL_1H;
+      fcc->tc.templ.exec_size = GEN6_EXECSIZE_16;
    }
    else {
-      fcc->tc.templ.qtr_ctrl = GEN6_COMPRESSION_1Q;
-      fcc->tc.templ.exec_size = BRW_EXECUTE_8;
+      fcc->tc.templ.qtr_ctrl = GEN6_QTRCTRL_1Q;
+      fcc->tc.templ.exec_size = GEN6_EXECSIZE_8;
    }
 
    fcc->tc.rect_linear_width = 8;
@@ -1802,7 +1802,7 @@ fs_setup(struct fs_compile_context *fcc,
     * The classic driver uses the sampler cache (gen6) or the data cache
     * (gen7).  Why?
     */
-   fcc->const_cache = GEN6_SFID_DATAPORT_CONSTANT_CACHE;
+   fcc->const_cache = GEN6_SFID_DP_CC;
 
    if (!fs_setup_tgsi(&fcc->tc, state->info.tokens, &fcc->tgsi)) {
       toy_compiler_cleanup(&fcc->tc);
@@ -1845,9 +1845,9 @@ fs_setup(struct fs_compile_context *fcc,
    fcc->first_free_mrf = 1;
    fcc->last_free_mrf = 15;
 
-   /* instructions are compressed with BRW_EXECUTE_16 */
+   /* instructions are compressed with GEN6_EXECSIZE_16 */
    fcc->num_grf_per_vrf =
-      (fcc->dispatch_mode == GEN6_WM_16_DISPATCH_ENABLE) ? 2 : 1;
+      (fcc->dispatch_mode == GEN6_WM_DW5_16_PIXEL_DISPATCH) ? 2 : 1;
 
    if (fcc->tc.dev->gen >= ILO_GEN(7)) {
       fcc->last_free_grf -= 15;
@@ -1858,7 +1858,7 @@ fs_setup(struct fs_compile_context *fcc,
    fcc->shader->in.start_grf = fcc->first_const_grf;
    fcc->shader->has_kill = fcc->tgsi.uses_kill;
    fcc->shader->dispatch_16 =
-      (fcc->dispatch_mode == GEN6_WM_16_DISPATCH_ENABLE);
+      (fcc->dispatch_mode == GEN6_WM_DW5_16_PIXEL_DISPATCH);
 
    return true;
 }
diff --git a/src/gallium/drivers/ilo/shader/ilo_shader_gs.c b/src/gallium/drivers/ilo/shader/ilo_shader_gs.c
index 0741754..91c300b 100644
--- a/src/gallium/drivers/ilo/shader/ilo_shader_gs.c
+++ b/src/gallium/drivers/ilo/shader/ilo_shader_gs.c
@@ -114,8 +114,8 @@ gs_COPY8(struct toy_compiler *tc, struct toy_dst dst, struct toy_src src)
    struct toy_inst *inst;
 
    inst = tc_MOV(tc, dst, src);
-   inst->exec_size = BRW_EXECUTE_8;
-   inst->mask_ctrl = BRW_MASK_DISABLE;
+   inst->exec_size = GEN6_EXECSIZE_8;
+   inst->mask_ctrl = GEN6_MASKCTRL_NOMASK;
 }
 
 static void
@@ -128,8 +128,8 @@ gs_COPY4(struct toy_compiler *tc,
    inst = tc_MOV(tc,
          tdst_offset(dst, 0, dst_ch),
          tsrc_offset(src, 0, src_ch));
-   inst->exec_size = BRW_EXECUTE_4;
-   inst->mask_ctrl = BRW_MASK_DISABLE;
+   inst->exec_size = GEN6_EXECSIZE_4;
+   inst->mask_ctrl = GEN6_MASKCTRL_NOMASK;
 }
 
 static void
@@ -142,8 +142,8 @@ gs_COPY1(struct toy_compiler *tc,
    inst = tc_MOV(tc,
          tdst_offset(dst, 0, dst_ch),
          tsrc_rect(tsrc_offset(src, 0, src_ch), TOY_RECT_010));
-   inst->exec_size = BRW_EXECUTE_1;
-   inst->mask_ctrl = BRW_MASK_DISABLE;
+   inst->exec_size = GEN6_EXECSIZE_1;
+   inst->mask_ctrl = GEN6_MASKCTRL_NOMASK;
 }
 
 static void
@@ -161,13 +161,13 @@ gs_init_vars(struct gs_compile_context *gcc)
    gcc->vars.prim_end = false;
    switch (gcc->out_vue_min_count) {
    case 1:
-      gcc->vars.prim_type = _3DPRIM_POINTLIST;
+      gcc->vars.prim_type = GEN6_3DPRIM_POINTLIST;
       break;
    case 2:
-      gcc->vars.prim_type = _3DPRIM_LINESTRIP;
+      gcc->vars.prim_type = GEN6_3DPRIM_LINESTRIP;
       break;
    case 3:
-      gcc->vars.prim_type = _3DPRIM_TRISTRIP;
+      gcc->vars.prim_type = GEN6_3DPRIM_TRISTRIP;
       break;
    }
 
@@ -212,11 +212,11 @@ gs_write_so(struct gs_compile_context *gcc,
    desc = tsrc_imm_mdesc_data_port(tc, false,
          1, send_write_commit_message,
          true, send_write_commit_message,
-         GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE, 0,
+         GEN6_MSG_DP_SVB_WRITE, 0,
          binding_table_index);
 
    tc_SEND(tc, dst, tsrc_from(mrf_header), desc,
-         GEN6_SFID_DATAPORT_RENDER_CACHE);
+         GEN6_SFID_DP_RC);
 }
 
 static void
@@ -262,12 +262,12 @@ gs_write_vue(struct gs_compile_context *gcc,
       if (complete) {
          desc = tsrc_imm_mdesc_urb(tc,
                eot, msg_len, !eot, true, true, !eot,
-               BRW_URB_SWIZZLE_NONE, sent, 0);
+               false, sent, 0);
       }
       else {
          desc = tsrc_imm_mdesc_urb(tc,
                false, msg_len, 0, false, true, false,
-               BRW_URB_SWIZZLE_NONE, sent, 0);
+               false, sent, 0);
       }
 
       tc_add2(tc, TOY_OPCODE_URB_WRITE,
@@ -323,9 +323,9 @@ gs_ff_sync(struct gs_compile_context *gcc, struct toy_dst dst,
    allocate = true;
    desc = tsrc_imm_mdesc_urb(tc, false, 1, 1,
          false, false, allocate,
-         BRW_URB_SWIZZLE_NONE, 0, 1);
+         false, 0, 1);
 
-   tc_SEND(tc, dst, tsrc_from(mrf_header), desc, BRW_SFID_URB);
+   tc_SEND(tc, dst, tsrc_from(mrf_header), desc, GEN6_SFID_URB);
 }
 
 static void
@@ -341,7 +341,7 @@ gs_discard(struct gs_compile_context *gcc)
 
    desc = tsrc_imm_mdesc_urb(tc,
          true, 1, 0, true, false, false,
-         BRW_URB_SWIZZLE_NONE, 0, 0);
+         false, 0, 0);
 
    tc_add2(tc, TOY_OPCODE_URB_WRITE,
          tdst_null(), tsrc_from(mrf_header), desc);
@@ -374,7 +374,7 @@ gs_lower_opcode_emit_so_dynamic(struct gs_compile_context *gcc)
    tc_IF(tc, tdst_null(),
          tsrc_from(gcc->dynamic_data.num_vertices_in_prim),
          tsrc_imm_d(gcc->out_vue_min_count),
-         BRW_CONDITIONAL_GE);
+         GEN6_COND_GE);
 
    {
       tc_ADD(tc, gcc->vars.tmp, tsrc_from(gcc->vars.so_index), tsrc_imm_d(0x03020100));
@@ -407,7 +407,7 @@ gs_lower_opcode_emit_vue_static(struct gs_compile_context *gcc)
             tsrc_imm_d(gcc->vars.prim_type << 2 |
                        gcc->vars.prim_start << 1 |
                        gcc->vars.prim_end));
-      inst2->exec_size = BRW_EXECUTE_1;
+      inst2->exec_size = GEN6_EXECSIZE_1;
       inst2->src[0] = tsrc_rect(inst2->src[0], TOY_RECT_010);
       inst2->src[1] = tsrc_rect(inst2->src[1], TOY_RECT_010);
    }
@@ -443,8 +443,8 @@ gs_lower_opcode_emit_so_static(struct gs_compile_context *gcc)
       return;
 
    inst = tc_MOV(tc, tdst_w(gcc->vars.tmp), tsrc_imm_v(0x03020100));
-   inst->exec_size = BRW_EXECUTE_8;
-   inst->mask_ctrl = BRW_MASK_DISABLE;
+   inst->exec_size = GEN6_EXECSIZE_8;
+   inst->mask_ctrl = GEN6_MASKCTRL_NOMASK;
 
    tc_ADD(tc, tdst_d(gcc->vars.tmp), tsrc_from(tdst_d(gcc->vars.tmp)),
          tsrc_rect(tsrc_from(gcc->vars.so_index), TOY_RECT_010));
@@ -452,7 +452,7 @@ gs_lower_opcode_emit_so_static(struct gs_compile_context *gcc)
    tc_IF(tc, tdst_null(),
          tsrc_rect(tsrc_offset(tsrc_from(tdst_d(gcc->vars.tmp)), 0, gcc->out_vue_min_count - 1), TOY_RECT_010),
          tsrc_rect(tsrc_offset(gcc->payload.svbi, 0, 4), TOY_RECT_010),
-         BRW_CONDITIONAL_LE);
+         GEN6_COND_LE);
    {
       for (i = 0; i < gcc->out_vue_min_count; i++) {
          for (j = 0; j < gcc->so_info->num_outputs; j++) {
@@ -594,31 +594,31 @@ gs_lower_opcode_tgsi_in(struct gs_compile_context *gcc,
       return;
    }
 
-   /* fix vertex ordering for _3DPRIM_TRISTRIP_REVERSE */
+   /* fix vertex ordering for GEN6_3DPRIM_TRISTRIP_REVERSE */
    if (gcc->in_vue_count == 3 && dim < 2) {
       struct toy_inst *inst;
 
       /* get PrimType */
       inst = tc_AND(tc, tdst_d(gcc->vars.tmp),
             tsrc_offset(gcc->payload.header, 0, 2), tsrc_imm_d(0x1f));
-      inst->exec_size = BRW_EXECUTE_1;
+      inst->exec_size = GEN6_EXECSIZE_1;
       inst->src[0] = tsrc_rect(inst->src[0], TOY_RECT_010);
       inst->src[1] = tsrc_rect(inst->src[1], TOY_RECT_010);
 
       inst = tc_CMP(tc, tdst_null(), tsrc_from(tdst_d(gcc->vars.tmp)),
-            tsrc_imm_d(_3DPRIM_TRISTRIP_REVERSE), BRW_CONDITIONAL_NEQ);
+            tsrc_imm_d(GEN6_3DPRIM_TRISTRIP_REVERSE), GEN6_COND_NZ);
       inst->src[0] = tsrc_rect(inst->src[0], TOY_RECT_010);
 
       attr = tsrc_offset(gcc->payload.vues[dim], reg, subreg);
       inst = tc_MOV(tc, dst, attr);
-      inst->pred_ctrl = BRW_PREDICATE_NORMAL;
+      inst->pred_ctrl = GEN6_PREDCTRL_NORMAL;
 
-      /* swap IN[0] and IN[1] for _3DPRIM_TRISTRIP_REVERSE */
+      /* swap IN[0] and IN[1] for GEN6_3DPRIM_TRISTRIP_REVERSE */
       dim = !dim;
 
       attr = tsrc_offset(gcc->payload.vues[dim], reg, subreg);
       inst = tc_MOV(tc, dst, attr);
-      inst->pred_ctrl = BRW_PREDICATE_NORMAL;
+      inst->pred_ctrl = GEN6_PREDCTRL_NORMAL;
       inst->pred_inv = true;
    }
    else {
@@ -645,7 +645,7 @@ gs_lower_opcode_tgsi_imm(struct gs_compile_context *gcc,
       inst = tc_MOV(&gcc->tc,
             tdst_writemask(tdst_ud(dst), 1 << ch),
             tsrc_imm_ud(imm[ch]));
-      inst->access_mode = BRW_ALIGN_16;
+      inst->access_mode = GEN6_ALIGN_16;
    }
 }
 
@@ -773,7 +773,7 @@ gs_lower_virtual_opcodes(struct gs_compile_context *gcc)
          toy_compiler_lower_math(tc, inst);
          break;
       case TOY_OPCODE_URB_WRITE:
-         toy_compiler_lower_to_send(tc, inst, false, BRW_SFID_URB);
+         toy_compiler_lower_to_send(tc, inst, false, GEN6_SFID_URB);
          break;
       default:
          if (inst->opcode > 127)
@@ -798,16 +798,16 @@ get_num_prims_static(struct gs_compile_context *gcc)
    tc_head(tc);
    while ((inst = tc_next_no_skip(tc)) != NULL) {
       switch (inst->opcode) {
-      case BRW_OPCODE_IF:
+      case GEN6_OPCODE_IF:
          if_depth++;
          break;
-      case BRW_OPCODE_ENDIF:
+      case GEN6_OPCODE_ENDIF:
          if_depth--;
          break;
       case TOY_OPCODE_DO:
          do_depth++;
          break;
-      case BRW_OPCODE_WHILE:
+      case GEN6_OPCODE_WHILE:
          do_depth--;
          break;
       case TOY_OPCODE_EMIT:
@@ -1265,8 +1265,8 @@ gs_setup(struct gs_compile_context *gcc,
    gcc->write_so = (state->info.stream_output.num_outputs > 0);
    gcc->write_vue = !gcc->variant->u.gs.rasterizer_discard;
 
-   gcc->tc.templ.access_mode = BRW_ALIGN_16;
-   gcc->tc.templ.exec_size = BRW_EXECUTE_4;
+   gcc->tc.templ.access_mode = GEN6_ALIGN_16;
+   gcc->tc.templ.exec_size = GEN6_EXECSIZE_4;
    gcc->tc.rect_linear_width = 4;
 
    if (state->info.tokens) {
@@ -1331,7 +1331,7 @@ gs_setup(struct gs_compile_context *gcc,
       }
    }
 
-   gcc->tc.templ.access_mode = BRW_ALIGN_1;
+   gcc->tc.templ.access_mode = GEN6_ALIGN_1;
 
    gs_setup_shader_in(gcc->shader, gcc->variant);
    gs_setup_shader_out(gcc->shader, &gcc->tgsi, false, gcc->output_map);
diff --git a/src/gallium/drivers/ilo/shader/ilo_shader_vs.c b/src/gallium/drivers/ilo/shader/ilo_shader_vs.c
index c20ecc6..c8a59e4 100644
--- a/src/gallium/drivers/ilo/shader/ilo_shader_vs.c
+++ b/src/gallium/drivers/ilo/shader/ilo_shader_vs.c
@@ -41,7 +41,7 @@ struct vs_compile_context {
 
    struct toy_compiler tc;
    struct toy_tgsi tgsi;
-   enum brw_message_target const_cache;
+   int const_cache;
 
    int output_map[PIPE_MAX_SHADER_OUTPUTS];
 
@@ -121,13 +121,13 @@ vs_lower_opcode_tgsi_const_gen6(struct vs_compile_context *vcc,
 
    /* set message header */
    inst = tc_MOV(tc, header, r0);
-   inst->mask_ctrl = BRW_MASK_DISABLE;
+   inst->mask_ctrl = GEN6_MASKCTRL_NOMASK;
 
    /* set block offsets */
    tc_MOV(tc, block_offsets, idx);
 
-   msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
-   msg_ctrl = BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD << 8;;
+   msg_type = GEN6_MSG_DP_OWORD_DUAL_BLOCK_READ;
+   msg_ctrl = GEN6_MSG_DP_OWORD_DUAL_BLOCK_SIZE_1;;
    msg_len = 2;
 
    desc = tsrc_imm_mdesc_data_port(tc, false, msg_len, 1, true, false,
@@ -160,12 +160,12 @@ vs_lower_opcode_tgsi_const_gen7(struct vs_compile_context *vcc,
    tc_MOV(tc, offset, idx);
 
    desc = tsrc_imm_mdesc_sampler(tc, 1, 1, false,
-         BRW_SAMPLER_SIMD_MODE_SIMD4X2,
-         GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
+         GEN6_MSG_SAMPLER_SIMD4X2,
+         GEN6_MSG_SAMPLER_LD,
          0,
          ILO_VS_CONST_SURFACE(dim));
 
-   tc_SEND(tc, dst, tsrc_from(offset), desc, BRW_SFID_SAMPLER);
+   tc_SEND(tc, dst, tsrc_from(offset), desc, GEN6_SFID_SAMPLER);
 }
 
 static void
@@ -334,12 +334,12 @@ vs_add_sampler_params(struct toy_compiler *tc, int msg_type, int base_mrf,
       m[i] = tdst(TOY_FILE_MRF, base_mrf + i, 0);
 
    switch (msg_type) {
-   case GEN5_SAMPLER_MESSAGE_SAMPLE_LOD:
+   case GEN6_MSG_SAMPLER_SAMPLE_L:
       tc_MOV(tc, tdst_writemask(m[0], coords_writemask), coords);
       tc_MOV(tc, tdst_writemask(m[1], TOY_WRITEMASK_X), bias_or_lod);
       num_params = 5;
       break;
-   case GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS:
+   case GEN6_MSG_SAMPLER_SAMPLE_D:
       tc_MOV(tc, tdst_writemask(m[0], coords_writemask), coords);
       tc_MOV(tc, tdst_writemask(m[1], TOY_WRITEMASK_XZ),
             tsrc_swizzle(ddx, 0, 0, 1, 1));
@@ -353,13 +353,13 @@ vs_add_sampler_params(struct toy_compiler *tc, int msg_type, int base_mrf,
       }
       num_params = 4 + num_derivs * 2;
       break;
-   case GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE:
+   case GEN6_MSG_SAMPLER_SAMPLE_L_C:
       tc_MOV(tc, tdst_writemask(m[0], coords_writemask), coords);
       tc_MOV(tc, tdst_writemask(m[1], TOY_WRITEMASK_X), ref_or_si);
       tc_MOV(tc, tdst_writemask(m[1], TOY_WRITEMASK_Y), bias_or_lod);
       num_params = 6;
       break;
-   case GEN5_SAMPLER_MESSAGE_SAMPLE_LD:
+   case GEN6_MSG_SAMPLER_LD:
       assert(num_coords <= 3);
       tc_MOV(tc, tdst_writemask(tdst_d(m[0]), coords_writemask), coords);
       tc_MOV(tc, tdst_writemask(tdst_d(m[0]), TOY_WRITEMASK_W), bias_or_lod);
@@ -371,7 +371,7 @@ vs_add_sampler_params(struct toy_compiler *tc, int msg_type, int base_mrf,
          num_params = 5;
       }
       break;
-   case GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO:
+   case GEN6_MSG_SAMPLER_RESINFO:
       tc_MOV(tc, tdst_writemask(tdst_d(m[0]), TOY_WRITEMASK_X), bias_or_lod);
       num_params = 1;
       break;
@@ -396,7 +396,7 @@ vs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst,
    int num_coords, ref_pos, num_derivs;
    int sampler_src;
 
-   simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD4X2;
+   simd_mode = GEN6_MSG_SAMPLER_SIMD4X2;
 
    coords = inst->src[0];
    ddx = tsrc_null();
@@ -414,14 +414,14 @@ vs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst,
       if (ref_pos >= 0) {
          assert(ref_pos < 4);
 
-         msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
+         msg_type = GEN7_MSG_SAMPLER_SAMPLE_D_C;
          ref_or_si = tsrc_swizzle1(coords, ref_pos);
 
          if (tc->dev->gen < ILO_GEN(7.5))
             tc_fail(tc, "TXD with shadow sampler not supported");
       }
       else {
-         msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
+         msg_type = GEN6_MSG_SAMPLER_SAMPLE_D;
       }
 
       ddx = inst->src[1];
@@ -433,17 +433,17 @@ vs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst,
       if (ref_pos >= 0) {
          assert(ref_pos < 3);
 
-         msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
+         msg_type = GEN6_MSG_SAMPLER_SAMPLE_L_C;
          ref_or_si = tsrc_swizzle1(coords, ref_pos);
       }
       else {
-         msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
+         msg_type = GEN6_MSG_SAMPLER_SAMPLE_L;
       }
 
       bias_or_lod = tsrc_swizzle1(coords, TOY_SWIZZLE_W);
       break;
    case TOY_OPCODE_TGSI_TXF:
-      msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
+      msg_type = GEN6_MSG_SAMPLER_LD;
 
       switch (inst->tex.target) {
       case TGSI_TEXTURE_2D_MSAA:
@@ -470,12 +470,12 @@ vs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst,
       sampler_src = 1;
       break;
    case TOY_OPCODE_TGSI_TXQ:
-      msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
+      msg_type = GEN6_MSG_SAMPLER_RESINFO;
       num_coords = 0;
       bias_or_lod = tsrc_swizzle1(coords, TOY_SWIZZLE_X);
       break;
    case TOY_OPCODE_TGSI_TXQ_LZ:
-      msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
+      msg_type = GEN6_MSG_SAMPLER_RESINFO;
       num_coords = 0;
       sampler_src = 0;
       break;
@@ -483,11 +483,11 @@ vs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst,
       if (ref_pos >= 0) {
          assert(ref_pos < 4);
 
-         msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
+         msg_type = GEN6_MSG_SAMPLER_SAMPLE_L_C;
          ref_or_si = tsrc_swizzle1(coords, ref_pos);
       }
       else {
-         msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
+         msg_type = GEN6_MSG_SAMPLER_SAMPLE_L;
       }
 
       bias_or_lod = tsrc_swizzle1(inst->src[1], TOY_SWIZZLE_X);
@@ -529,8 +529,8 @@ vs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst,
          for (i = 0; i < 3; i++)
             abs_coords[i] = tsrc_absolute(tsrc_swizzle1(coords, i));
 
-         tc_SEL(tc, max, abs_coords[0], abs_coords[0], BRW_CONDITIONAL_GE);
-         tc_SEL(tc, max, tsrc_from(max), abs_coords[0], BRW_CONDITIONAL_GE);
+         tc_SEL(tc, max, abs_coords[0], abs_coords[0], GEN6_COND_GE);
+         tc_SEL(tc, max, tsrc_from(max), abs_coords[0], GEN6_COND_GE);
          tc_INV(tc, max, tsrc_from(max));
 
          for (i = 0; i < 3; i++)
@@ -588,7 +588,7 @@ vs_lower_opcode_tgsi_sampling(struct vs_compile_context *vcc,
       break;
    }
 
-   toy_compiler_lower_to_send(tc, inst, false, BRW_SFID_SAMPLER);
+   toy_compiler_lower_to_send(tc, inst, false, GEN6_SFID_SAMPLER);
    inst->src[0] = tsrc(TOY_FILE_MRF, vcc->first_free_mrf, 0);
    inst->src[1] = desc;
 
@@ -649,7 +649,7 @@ static void
 vs_lower_opcode_urb_write(struct toy_compiler *tc, struct toy_inst *inst)
 {
    /* vs_write_vue() has set up the message registers */
-   toy_compiler_lower_to_send(tc, inst, false, BRW_SFID_URB);
+   toy_compiler_lower_to_send(tc, inst, false, GEN6_SFID_URB);
 }
 
 static void
@@ -915,15 +915,15 @@ vs_write_vue(struct vs_compile_context *vcc)
    header = tdst_ud(tdst(TOY_FILE_MRF, vcc->first_free_mrf, 0));
    r0 = tsrc_ud(tsrc(TOY_FILE_GRF, 0, 0));
    inst = tc_MOV(tc, header, r0);
-   inst->mask_ctrl = BRW_MASK_DISABLE;
+   inst->mask_ctrl = GEN6_MASKCTRL_NOMASK;
 
    if (tc->dev->gen >= ILO_GEN(7)) {
       inst = tc_OR(tc, tdst_offset(header, 0, 5),
             tsrc_rect(tsrc_offset(r0, 0, 5), TOY_RECT_010),
             tsrc_rect(tsrc_imm_ud(0xff00), TOY_RECT_010));
-      inst->exec_size = BRW_EXECUTE_1;
-      inst->access_mode = BRW_ALIGN_1;
-      inst->mask_ctrl = BRW_MASK_DISABLE;
+      inst->exec_size = GEN6_EXECSIZE_1;
+      inst->access_mode = GEN6_ALIGN_1;
+      inst->mask_ctrl = GEN6_MASKCTRL_NOMASK;
    }
 
    total_attrs = vs_collect_outputs(vcc, outs);
@@ -986,7 +986,7 @@ vs_write_vue(struct vs_compile_context *vcc)
 
       assert(sent_attrs % 2 == 0);
       desc = tsrc_imm_mdesc_urb(tc, eot, msg_len, 0,
-            eot, true, false, BRW_URB_SWIZZLE_INTERLEAVE, sent_attrs / 2, 0);
+            eot, true, false, true, sent_attrs / 2, 0);
 
       tc_add2(tc, TOY_OPCODE_URB_WRITE, tdst_null(), tsrc_from(header), desc);
 
@@ -1216,15 +1216,15 @@ vs_setup(struct vs_compile_context *vcc,
    vcc->variant = variant;
 
    toy_compiler_init(&vcc->tc, state->info.dev);
-   vcc->tc.templ.access_mode = BRW_ALIGN_16;
-   vcc->tc.templ.exec_size = BRW_EXECUTE_8;
+   vcc->tc.templ.access_mode = GEN6_ALIGN_16;
+   vcc->tc.templ.exec_size = GEN6_EXECSIZE_8;
    vcc->tc.rect_linear_width = 4;
 
    /*
     * The classic driver uses the sampler cache (gen6) or the data cache
     * (gen7).  Why?
     */
-   vcc->const_cache = GEN6_SFID_DATAPORT_CONSTANT_CACHE;
+   vcc->const_cache = GEN6_SFID_DP_CC;
 
    if (!vs_setup_tgsi(&vcc->tc, state->info.tokens, &vcc->tgsi)) {
       toy_compiler_cleanup(&vcc->tc);
diff --git a/src/gallium/drivers/ilo/shader/toy_compiler.c b/src/gallium/drivers/ilo/shader/toy_compiler.c
index 623d478..6e9dac1 100644
--- a/src/gallium/drivers/ilo/shader/toy_compiler.c
+++ b/src/gallium/drivers/ilo/shader/toy_compiler.c
@@ -71,30 +71,30 @@ tc_dump_operand(struct toy_compiler *tc,
       break;
    case TOY_FILE_ARF:
       switch (reg) {
-      case BRW_ARF_NULL:
+      case GEN6_ARF_NULL:
          ilo_printf("null");
          break;
-      case BRW_ARF_ADDRESS:
+      case GEN6_ARF_A0:
          ilo_printf("a0.%d", subreg);
          break;
-      case BRW_ARF_ACCUMULATOR:
-      case BRW_ARF_ACCUMULATOR + 1:
+      case GEN6_ARF_ACC0:
+      case GEN6_ARF_ACC0 + 1:
          ilo_printf("acc%d.%d", (reg & 1), subreg);
          break;
-      case BRW_ARF_FLAG:
+      case GEN6_ARF_F0:
          ilo_printf("f0.%d", subreg);
          break;
-      case BRW_ARF_STATE:
+      case GEN6_ARF_SR0:
          ilo_printf("sr0.%d", subreg);
          break;
-      case BRW_ARF_CONTROL:
+      case GEN6_ARF_CR0:
          ilo_printf("cr0.%d", subreg);
          break;
-      case BRW_ARF_NOTIFICATION_COUNT:
-      case BRW_ARF_NOTIFICATION_COUNT + 1:
+      case GEN6_ARF_N0:
+      case GEN6_ARF_N0 + 1:
          ilo_printf("n%d.%d", (reg & 1), subreg);
          break;
-      case BRW_ARF_IP:
+      case GEN6_ARF_IP:
          ilo_printf("ip");
          break;
       }
@@ -259,59 +259,59 @@ static const char *
 get_opcode_name(unsigned opcode)
 {
    switch (opcode) {
-   case BRW_OPCODE_MOV:                   return "mov";
-   case BRW_OPCODE_SEL:                   return "sel";
-   case BRW_OPCODE_NOT:                   return "not";
-   case BRW_OPCODE_AND:                   return "and";
-   case BRW_OPCODE_OR:                    return "or";
-   case BRW_OPCODE_XOR:                   return "xor";
-   case BRW_OPCODE_SHR:                   return "shr";
-   case BRW_OPCODE_SHL:                   return "shl";
-   case BRW_OPCODE_RSR:                   return "rsr";
-   case BRW_OPCODE_RSL:                   return "rsl";
-   case BRW_OPCODE_ASR:                   return "asr";
-   case BRW_OPCODE_CMP:                   return "cmp";
-   case BRW_OPCODE_CMPN:                  return "cmpn";
-   case BRW_OPCODE_JMPI:                  return "jmpi";
-   case BRW_OPCODE_IF:                    return "if";
-   case BRW_OPCODE_IFF:                   return "iff";
-   case BRW_OPCODE_ELSE:                  return "else";
-   case BRW_OPCODE_ENDIF:                 return "endif";
-   case BRW_OPCODE_DO:                    return "do";
-   case BRW_OPCODE_WHILE:                 return "while";
-   case BRW_OPCODE_BREAK:                 return "break";
-   case BRW_OPCODE_CONTINUE:              return "continue";
-   case BRW_OPCODE_HALT:                  return "halt";
-   case BRW_OPCODE_MSAVE:                 return "msave";
-   case BRW_OPCODE_MRESTORE:              return "mrestore";
-   case BRW_OPCODE_PUSH:                  return "push";
-   case BRW_OPCODE_POP:                   return "pop";
-   case BRW_OPCODE_WAIT:                  return "wait";
-   case BRW_OPCODE_SEND:                  return "send";
-   case BRW_OPCODE_SENDC:                 return "sendc";
-   case BRW_OPCODE_MATH:                  return "math";
-   case BRW_OPCODE_ADD:                   return "add";
-   case BRW_OPCODE_MUL:                   return "mul";
-   case BRW_OPCODE_AVG:                   return "avg";
-   case BRW_OPCODE_FRC:                   return "frc";
-   case BRW_OPCODE_RNDU:                  return "rndu";
-   case BRW_OPCODE_RNDD:                  return "rndd";
-   case BRW_OPCODE_RNDE:                  return "rnde";
-   case BRW_OPCODE_RNDZ:                  return "rndz";
-   case BRW_OPCODE_MAC:                   return "mac";
-   case BRW_OPCODE_MACH:                  return "mach";
-   case BRW_OPCODE_LZD:                   return "lzd";
-   case BRW_OPCODE_SAD2:                  return "sad2";
-   case BRW_OPCODE_SADA2:                 return "sada2";
-   case BRW_OPCODE_DP4:                   return "dp4";
-   case BRW_OPCODE_DPH:                   return "dph";
-   case BRW_OPCODE_DP3:                   return "dp3";
-   case BRW_OPCODE_DP2:                   return "dp2";
-   case BRW_OPCODE_DPA2:                  return "dpa2";
-   case BRW_OPCODE_LINE:                  return "line";
-   case BRW_OPCODE_PLN:                   return "pln";
-   case BRW_OPCODE_MAD:                   return "mad";
-   case BRW_OPCODE_NOP:                   return "nop";
+   case GEN6_OPCODE_MOV:                   return "mov";
+   case GEN6_OPCODE_SEL:                   return "sel";
+   case GEN6_OPCODE_NOT:                   return "not";
+   case GEN6_OPCODE_AND:                   return "and";
+   case GEN6_OPCODE_OR:                    return "or";
+   case GEN6_OPCODE_XOR:                   return "xor";
+   case GEN6_OPCODE_SHR:                   return "shr";
+   case GEN6_OPCODE_SHL:                   return "shl";
+   case 0xa:                   return "rsr";
+   case 0xb:                   return "rsl";
+   case GEN6_OPCODE_ASR:                   return "asr";
+   case GEN6_OPCODE_CMP:                   return "cmp";
+   case GEN6_OPCODE_CMPN:                  return "cmpn";
+   case GEN6_OPCODE_JMPI:                  return "jmpi";
+   case GEN6_OPCODE_IF:                    return "if";
+   case 0x23:                   return "iff";
+   case GEN6_OPCODE_ELSE:                  return "else";
+   case GEN6_OPCODE_ENDIF:                 return "endif";
+   case 0x26:                    return "do";
+   case GEN6_OPCODE_WHILE:                 return "while";
+   case GEN6_OPCODE_BREAK:                 return "break";
+   case GEN6_OPCODE_CONT:              return "continue";
+   case GEN6_OPCODE_HALT:                  return "halt";
+   case 0x2c:                 return "msave";
+   case 0x2d:              return "mrestore";
+   case 0x2e:                  return "push";
+   case 0x2f:                   return "pop";
+   case GEN6_OPCODE_WAIT:                  return "wait";
+   case GEN6_OPCODE_SEND:                  return "send";
+   case GEN6_OPCODE_SENDC:                 return "sendc";
+   case GEN6_OPCODE_MATH:                  return "math";
+   case GEN6_OPCODE_ADD:                   return "add";
+   case GEN6_OPCODE_MUL:                   return "mul";
+   case GEN6_OPCODE_AVG:                   return "avg";
+   case GEN6_OPCODE_FRC:                   return "frc";
+   case GEN6_OPCODE_RNDU:                  return "rndu";
+   case GEN6_OPCODE_RNDD:                  return "rndd";
+   case GEN6_OPCODE_RNDE:                  return "rnde";
+   case GEN6_OPCODE_RNDZ:                  return "rndz";
+   case GEN6_OPCODE_MAC:                   return "mac";
+   case GEN6_OPCODE_MACH:                  return "mach";
+   case GEN6_OPCODE_LZD:                   return "lzd";
+   case GEN6_OPCODE_SAD2:                  return "sad2";
+   case GEN6_OPCODE_SADA2:                 return "sada2";
+   case GEN6_OPCODE_DP4:                   return "dp4";
+   case GEN6_OPCODE_DPH:                   return "dph";
+   case GEN6_OPCODE_DP3:                   return "dp3";
+   case GEN6_OPCODE_DP2:                   return "dp2";
+   case 0x58:                  return "dpa2";
+   case GEN6_OPCODE_LINE:                  return "line";
+   case GEN6_OPCODE_PLN:                   return "pln";
+   case GEN6_OPCODE_MAD:                   return "mad";
+   case GEN6_OPCODE_NOP:                   return "nop";
    case TOY_OPCODE_DO:                    return "do";
    /* TGSI */
    case TOY_OPCODE_TGSI_IN:               return "tgsi.in";
@@ -373,47 +373,47 @@ static const char *
 get_cond_modifier_name(unsigned opcode, unsigned cond_modifier)
 {
    switch (opcode) {
-   case BRW_OPCODE_SEND:
-   case BRW_OPCODE_SENDC:
+   case GEN6_OPCODE_SEND:
+   case GEN6_OPCODE_SENDC:
       /* SFID */
       switch (cond_modifier) {
-      case BRW_SFID_NULL:                       return "Null";
-      case BRW_SFID_SAMPLER:                    return "Sampling Engine";
-      case BRW_SFID_MESSAGE_GATEWAY:            return "Message Gateway";
-      case GEN6_SFID_DATAPORT_SAMPLER_CACHE:    return "Data Port Sampler Cache";
-      case GEN6_SFID_DATAPORT_RENDER_CACHE:     return "Data Port Render Cache";
-      case BRW_SFID_URB:                        return "URB";
-      case BRW_SFID_THREAD_SPAWNER:             return "Thread Spawner";
-      case GEN6_SFID_DATAPORT_CONSTANT_CACHE:   return "Constant Cache";
+      case GEN6_SFID_NULL:                       return "Null";
+      case GEN6_SFID_SAMPLER:                    return "Sampling Engine";
+      case GEN6_SFID_GATEWAY:            return "Message Gateway";
+      case GEN6_SFID_DP_SAMPLER:    return "Data Port Sampler Cache";
+      case GEN6_SFID_DP_RC:     return "Data Port Render Cache";
+      case GEN6_SFID_URB:                        return "URB";
+      case GEN6_SFID_SPAWNER:             return "Thread Spawner";
+      case GEN6_SFID_DP_CC:   return "Constant Cache";
       default:                                  return "Unknown";
       }
       break;
-   case BRW_OPCODE_MATH:
+   case GEN6_OPCODE_MATH:
       /* FC */
       switch (cond_modifier) {
-      case BRW_MATH_FUNCTION_INV:               return "INV";
-      case BRW_MATH_FUNCTION_LOG:               return "LOG";
-      case BRW_MATH_FUNCTION_EXP:               return "EXP";
-      case BRW_MATH_FUNCTION_SQRT:              return "SQRT";
-      case BRW_MATH_FUNCTION_RSQ:               return "RSQ";
-      case BRW_MATH_FUNCTION_SIN:               return "SIN";
-      case BRW_MATH_FUNCTION_COS:               return "COS";
-      case BRW_MATH_FUNCTION_FDIV:              return "FDIV";
-      case BRW_MATH_FUNCTION_POW:               return "POW";
-      case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT:  return "INT DIV (quotient)";
-      case BRW_MATH_FUNCTION_INT_DIV_REMAINDER: return "INT DIV (remainder)";
+      case GEN6_MATH_INV:               return "INV";
+      case GEN6_MATH_LOG:               return "LOG";
+      case GEN6_MATH_EXP:               return "EXP";
+      case GEN6_MATH_SQRT:              return "SQRT";
+      case GEN6_MATH_RSQ:               return "RSQ";
+      case GEN6_MATH_SIN:               return "SIN";
+      case GEN6_MATH_COS:               return "COS";
+      case GEN6_MATH_FDIV:              return "FDIV";
+      case GEN6_MATH_POW:               return "POW";
+      case GEN6_MATH_INT_DIV_QUOTIENT:  return "INT DIV (quotient)";
+      case GEN6_MATH_INT_DIV_REMAINDER: return "INT DIV (remainder)";
       default:                                  return "UNK";
       }
       break;
    default:
       switch (cond_modifier) {
-      case BRW_CONDITIONAL_NONE:                return NULL;
-      case BRW_CONDITIONAL_Z:                   return "z";
-      case BRW_CONDITIONAL_NZ:                  return "nz";
-      case BRW_CONDITIONAL_G:                   return "g";
-      case BRW_CONDITIONAL_GE:                  return "ge";
-      case BRW_CONDITIONAL_L:                   return "l";
-      case BRW_CONDITIONAL_LE:                  return "le";
+      case GEN6_COND_NORMAL:                return NULL;
+      case GEN6_COND_Z:                   return "z";
+      case GEN6_COND_NZ:                  return "nz";
+      case GEN6_COND_G:                   return "g";
+      case GEN6_COND_GE:                  return "ge";
+      case GEN6_COND_L:                   return "l";
+      case GEN6_COND_LE:                  return "le";
       default:                                  return "unk";
       }
       break;
@@ -433,7 +433,7 @@ tc_dump_inst(struct toy_compiler *tc, const struct toy_inst *inst)
 
    ilo_printf("  %s", name);
 
-   if (inst->opcode == BRW_OPCODE_NOP) {
+   if (inst->opcode == GEN6_OPCODE_NOP) {
       ilo_printf("\n");
       return;
    }
@@ -506,16 +506,16 @@ tc_init_inst_templ(struct toy_compiler *tc)
    struct toy_inst *templ = &tc->templ;
    int i;
 
-   templ->opcode = BRW_OPCODE_NOP;
-   templ->access_mode = BRW_ALIGN_1;
-   templ->mask_ctrl = BRW_MASK_ENABLE;
-   templ->dep_ctrl = BRW_DEPENDENCY_NORMAL;
-   templ->qtr_ctrl = GEN6_COMPRESSION_1Q;
-   templ->thread_ctrl = BRW_THREAD_NORMAL;
-   templ->pred_ctrl = BRW_PREDICATE_NONE;
+   templ->opcode = GEN6_OPCODE_NOP;
+   templ->access_mode = GEN6_ALIGN_1;
+   templ->mask_ctrl = GEN6_MASKCTRL_NORMAL;
+   templ->dep_ctrl = GEN6_DEPCTRL_NORMAL;
+   templ->qtr_ctrl = GEN6_QTRCTRL_1Q;
+   templ->thread_ctrl = GEN6_THREADCTRL_NORMAL;
+   templ->pred_ctrl = GEN6_PREDCTRL_NONE;
    templ->pred_inv = false;
-   templ->exec_size = BRW_EXECUTE_1;
-   templ->cond_modifier = BRW_CONDITIONAL_NONE;
+   templ->exec_size = GEN6_EXECSIZE_1;
+   templ->cond_modifier = GEN6_COND_NORMAL;
    templ->acc_wr_ctrl = false;
    templ->saturate = false;
 
diff --git a/src/gallium/drivers/ilo/shader/toy_compiler.h b/src/gallium/drivers/ilo/shader/toy_compiler.h
index 372a2ac..c23d7fc 100644
--- a/src/gallium/drivers/ilo/shader/toy_compiler.h
+++ b/src/gallium/drivers/ilo/shader/toy_compiler.h
@@ -38,7 +38,7 @@
  * Toy opcodes.
  */
 enum toy_opcode {
-   /* 0..127 are reserved for BRW_OPCODE_x */
+   /* 0..127 are reserved for GEN6_OPCODE_x */
    TOY_OPCODE_LAST_HW = 127,
 
    TOY_OPCODE_DO,
@@ -108,15 +108,15 @@ enum toy_opcode {
  */
 struct toy_inst {
    unsigned opcode:8;            /* enum toy_opcode      */
-   unsigned access_mode:1;       /* BRW_ALIGN_x          */
-   unsigned mask_ctrl:1;         /* BRW_MASK_x           */
-   unsigned dep_ctrl:2;          /* BRW_DEPENDENCY_x     */
-   unsigned qtr_ctrl:2;          /* GEN6_COMPRESSION_x   */
-   unsigned thread_ctrl:2;       /* BRW_THREAD_x         */
-   unsigned pred_ctrl:4;         /* BRW_PREDICATE_x      */
+   unsigned access_mode:1;       /* GEN6_ALIGN_x          */
+   unsigned mask_ctrl:1;         /* GEN6_MASKCTRL_x           */
+   unsigned dep_ctrl:2;          /* GEN6_DEPCTRL_x     */
+   unsigned qtr_ctrl:2;          /* GEN6_QTRCTRL_x   */
+   unsigned thread_ctrl:2;       /* GEN6_THREADCTRL_x         */
+   unsigned pred_ctrl:4;         /* GEN6_PREDCTRL_x      */
    unsigned pred_inv:1;          /* true or false        */
-   unsigned exec_size:3;         /* BRW_EXECUTE_x        */
-   unsigned cond_modifier:4;     /* BRW_CONDITIONAL_x    */
+   unsigned exec_size:3;         /* GEN6_EXECSIZE_x        */
+   unsigned cond_modifier:4;     /* GEN6_COND_x    */
    unsigned acc_wr_ctrl:1;       /* true or false        */
    unsigned saturate:1;          /* true or false        */
 
@@ -351,30 +351,30 @@ func(struct toy_compiler *tc,             \
    return inst;                           \
 }
 
-TC_ALU0(tc_NOP, BRW_OPCODE_NOP)
-TC_ALU0(tc_ELSE, BRW_OPCODE_ELSE)
-TC_ALU0(tc_ENDIF, BRW_OPCODE_ENDIF)
-TC_ALU1(tc_MOV, BRW_OPCODE_MOV)
-TC_ALU1(tc_RNDD, BRW_OPCODE_RNDD)
+TC_ALU0(tc_NOP, GEN6_OPCODE_NOP)
+TC_ALU0(tc_ELSE, GEN6_OPCODE_ELSE)
+TC_ALU0(tc_ENDIF, GEN6_OPCODE_ENDIF)
+TC_ALU1(tc_MOV, GEN6_OPCODE_MOV)
+TC_ALU1(tc_RNDD, GEN6_OPCODE_RNDD)
 TC_ALU1(tc_INV, TOY_OPCODE_INV)
-TC_ALU1(tc_FRC, BRW_OPCODE_FRC)
+TC_ALU1(tc_FRC, GEN6_OPCODE_FRC)
 TC_ALU1(tc_EXP, TOY_OPCODE_EXP)
 TC_ALU1(tc_LOG, TOY_OPCODE_LOG)
-TC_ALU2(tc_ADD, BRW_OPCODE_ADD)
-TC_ALU2(tc_MUL, BRW_OPCODE_MUL)
-TC_ALU2(tc_AND, BRW_OPCODE_AND)
-TC_ALU2(tc_OR, BRW_OPCODE_OR)
-TC_ALU2(tc_DP2, BRW_OPCODE_DP2)
-TC_ALU2(tc_DP3, BRW_OPCODE_DP3)
-TC_ALU2(tc_DP4, BRW_OPCODE_DP4)
-TC_ALU2(tc_SHL, BRW_OPCODE_SHL)
-TC_ALU2(tc_SHR, BRW_OPCODE_SHR)
+TC_ALU2(tc_ADD, GEN6_OPCODE_ADD)
+TC_ALU2(tc_MUL, GEN6_OPCODE_MUL)
+TC_ALU2(tc_AND, GEN6_OPCODE_AND)
+TC_ALU2(tc_OR, GEN6_OPCODE_OR)
+TC_ALU2(tc_DP2, GEN6_OPCODE_DP2)
+TC_ALU2(tc_DP3, GEN6_OPCODE_DP3)
+TC_ALU2(tc_DP4, GEN6_OPCODE_DP4)
+TC_ALU2(tc_SHL, GEN6_OPCODE_SHL)
+TC_ALU2(tc_SHR, GEN6_OPCODE_SHR)
 TC_ALU2(tc_POW, TOY_OPCODE_POW)
-TC_ALU3(tc_MAC, BRW_OPCODE_MAC)
-TC_CND2(tc_SEL, BRW_OPCODE_SEL)
-TC_CND2(tc_CMP, BRW_OPCODE_CMP)
-TC_CND2(tc_IF, BRW_OPCODE_IF)
-TC_CND2(tc_SEND, BRW_OPCODE_SEND)
+TC_ALU3(tc_MAC, GEN6_OPCODE_MAC)
+TC_CND2(tc_SEL, GEN6_OPCODE_SEL)
+TC_CND2(tc_CMP, GEN6_OPCODE_CMP)
+TC_CND2(tc_IF, GEN6_OPCODE_IF)
+TC_CND2(tc_SEND, GEN6_OPCODE_SEND)
 
 /**
  * Upcast a list_head to an instruction.
diff --git a/src/gallium/drivers/ilo/shader/toy_compiler_asm.c b/src/gallium/drivers/ilo/shader/toy_compiler_asm.c
index 09a00dd..cf57a90 100644
--- a/src/gallium/drivers/ilo/shader/toy_compiler_asm.c
+++ b/src/gallium/drivers/ilo/shader/toy_compiler_asm.c
@@ -73,8 +73,8 @@ src_is_null(const struct codegen *cg, int idx)
 {
    const struct codegen_src *src = &cg->src[idx];
 
-   return (src->file == BRW_ARCHITECTURE_REGISTER_FILE &&
-           src->origin == BRW_ARF_NULL << CG_REG_SHIFT);
+   return (src->file == GEN6_FILE_ARF &&
+           src->origin == GEN6_ARF_NULL << CG_REG_SHIFT);
 }
 
 /**
@@ -87,7 +87,7 @@ translate_src(const struct codegen *cg, int idx)
    uint32_t dw;
 
    /* special treatment may be needed if any of the operand is immediate */
-   if (cg->src[0].file == BRW_IMMEDIATE_VALUE) {
+   if (cg->src[0].file == GEN6_FILE_IMM) {
       assert(!cg->src[0].absolute && !cg->src[0].negate);
       /* only the last src operand can be an immediate */
       assert(src_is_null(cg, 1));
@@ -97,22 +97,22 @@ translate_src(const struct codegen *cg, int idx)
       else
          return cg->src[0].origin;
    }
-   else if (idx && cg->src[1].file == BRW_IMMEDIATE_VALUE) {
+   else if (idx && cg->src[1].file == GEN6_FILE_IMM) {
       assert(!cg->src[1].absolute && !cg->src[1].negate);
       return cg->src[1].origin;
    }
 
-   assert(src->file != BRW_IMMEDIATE_VALUE);
+   assert(src->file != GEN6_FILE_IMM);
 
    if (src->indirect) {
       const int offset = (int) src->origin;
 
-      assert(src->file == BRW_GENERAL_REGISTER_FILE);
+      assert(src->file == GEN6_FILE_GRF);
       assert(offset < 512 && offset >= -512);
 
-      if (cg->inst->access_mode == BRW_ALIGN_16) {
-         assert(src->width == BRW_WIDTH_4);
-         assert(src->horz_stride == BRW_HORIZONTAL_STRIDE_1);
+      if (cg->inst->access_mode == GEN6_ALIGN_16) {
+         assert(src->width == GEN6_WIDTH_4);
+         assert(src->horz_stride == GEN6_HORZSTRIDE_1);
 
          /* the lower 4 bits are reserved for the swizzle_[xy] */
          assert(!(src->origin & 0xf));
@@ -120,7 +120,7 @@ translate_src(const struct codegen *cg, int idx)
          dw = src->vert_stride << 21 |
               src->swizzle[3] << 18 |
               src->swizzle[2] << 16 |
-              BRW_ADDRESS_REGISTER_INDIRECT_REGISTER << 15 |
+              GEN6_ADDRMODE_INDIRECT << 15 |
               src->negate << 14 |
               src->absolute << 13 |
               src->indirect_subreg << 10 |
@@ -137,7 +137,7 @@ translate_src(const struct codegen *cg, int idx)
          dw = src->vert_stride << 21 |
               src->width << 18 |
               src->horz_stride << 16 |
-              BRW_ADDRESS_REGISTER_INDIRECT_REGISTER << 15 |
+              GEN6_ADDRMODE_INDIRECT << 15 |
               src->negate << 14 |
               src->absolute << 13 |
               src->indirect_subreg << 10 |
@@ -146,25 +146,25 @@ translate_src(const struct codegen *cg, int idx)
    }
    else {
       switch (src->file) {
-      case BRW_ARCHITECTURE_REGISTER_FILE:
+      case GEN6_FILE_ARF:
          break;
-      case BRW_GENERAL_REGISTER_FILE:
+      case GEN6_FILE_GRF:
          assert(CG_REG_NUM(src->origin) < 128);
          break;
-      case BRW_MESSAGE_REGISTER_FILE:
-         assert(cg->inst->opcode == BRW_OPCODE_SEND ||
-                cg->inst->opcode == BRW_OPCODE_SENDC);
+      case GEN6_FILE_MRF:
+         assert(cg->inst->opcode == GEN6_OPCODE_SEND ||
+                cg->inst->opcode == GEN6_OPCODE_SENDC);
          assert(CG_REG_NUM(src->origin) < 16);
          break;
-      case BRW_IMMEDIATE_VALUE:
+      case GEN6_FILE_IMM:
       default:
          assert(!"invalid src file");
          break;
       }
 
-      if (cg->inst->access_mode == BRW_ALIGN_16) {
-         assert(src->width == BRW_WIDTH_4);
-         assert(src->horz_stride == BRW_HORIZONTAL_STRIDE_1);
+      if (cg->inst->access_mode == GEN6_ALIGN_16) {
+         assert(src->width == GEN6_WIDTH_4);
+         assert(src->horz_stride == GEN6_HORZSTRIDE_1);
 
          /* the lower 4 bits are reserved for the swizzle_[xy] */
          assert(!(src->origin & 0xf));
@@ -172,7 +172,7 @@ translate_src(const struct codegen *cg, int idx)
          dw = src->vert_stride << 21 |
               src->swizzle[3] << 18 |
               src->swizzle[2] << 16 |
-              BRW_ADDRESS_DIRECT << 15 |
+              GEN6_ADDRMODE_DIRECT << 15 |
               src->negate << 14 |
               src->absolute << 13 |
               src->origin |
@@ -188,7 +188,7 @@ translate_src(const struct codegen *cg, int idx)
          dw = src->vert_stride << 21 |
               src->width << 18 |
               src->horz_stride << 16 |
-              BRW_ADDRESS_DIRECT << 15 |
+              GEN6_ADDRMODE_DIRECT << 15 |
               src->negate << 14 |
               src->absolute << 13 |
               src->origin;
@@ -211,14 +211,14 @@ translate_dst_region(const struct codegen *cg)
    const struct codegen_dst *dst = &cg->dst;
    uint16_t dw1_region;
 
-   if (dst->file == BRW_IMMEDIATE_VALUE) {
+   if (dst->file == GEN6_FILE_IMM) {
       /* dst is immediate (JIP) when the opcode is a conditional branch */
       switch (cg->inst->opcode) {
-      case BRW_OPCODE_IF:
-      case BRW_OPCODE_ELSE:
-      case BRW_OPCODE_ENDIF:
-      case BRW_OPCODE_WHILE:
-         assert(dst->type == BRW_REGISTER_TYPE_W);
+      case GEN6_OPCODE_IF:
+      case GEN6_OPCODE_ELSE:
+      case GEN6_OPCODE_ENDIF:
+      case GEN6_OPCODE_WHILE:
+         assert(dst->type == GEN6_TYPE_W);
          dw1_region = (dst->origin & 0xffff);
          break;
       default:
@@ -233,21 +233,21 @@ translate_dst_region(const struct codegen *cg)
    if (dst->indirect) {
       const int offset = (int) dst->origin;
 
-      assert(dst->file == BRW_GENERAL_REGISTER_FILE);
+      assert(dst->file == GEN6_FILE_GRF);
       assert(offset < 512 && offset >= -512);
 
-      if (cg->inst->access_mode == BRW_ALIGN_16) {
+      if (cg->inst->access_mode == GEN6_ALIGN_16) {
          /*
           * From the Sandy Bridge PRM, volume 4 part 2, page 144:
           *
           *     "Allthough Dst.HorzStride is a don't care for Align16, HW
           *      needs this to be programmed as 01."
           */
-         assert(dst->horz_stride == BRW_HORIZONTAL_STRIDE_1);
+         assert(dst->horz_stride == GEN6_HORZSTRIDE_1);
          /* the lower 4 bits are reserved for the writemask */
          assert(!(dst->origin & 0xf));
 
-         dw1_region = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER << 15 |
+         dw1_region = GEN6_ADDRMODE_INDIRECT << 15 |
                       dst->horz_stride << 13 |
                       dst->indirect_subreg << 10 |
                       (dst->origin & 0x3f0) |
@@ -256,25 +256,25 @@ translate_dst_region(const struct codegen *cg)
       else {
          assert(dst->writemask == TOY_WRITEMASK_XYZW);
 
-         dw1_region = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER << 15 |
+         dw1_region = GEN6_ADDRMODE_INDIRECT << 15 |
                       dst->horz_stride << 13 |
                       dst->indirect_subreg << 10 |
                       (dst->origin & 0x3ff);
       }
    }
    else {
-      assert((dst->file == BRW_GENERAL_REGISTER_FILE &&
+      assert((dst->file == GEN6_FILE_GRF &&
               CG_REG_NUM(dst->origin) < 128) ||
-             (dst->file == BRW_MESSAGE_REGISTER_FILE &&
+             (dst->file == GEN6_FILE_MRF &&
               CG_REG_NUM(dst->origin) < 16) ||
-             (dst->file == BRW_ARCHITECTURE_REGISTER_FILE));
+             (dst->file == GEN6_FILE_ARF));
 
-      if (cg->inst->access_mode == BRW_ALIGN_16) {
+      if (cg->inst->access_mode == GEN6_ALIGN_16) {
          /* similar to the indirect case */
-         assert(dst->horz_stride == BRW_HORIZONTAL_STRIDE_1);
+         assert(dst->horz_stride == GEN6_HORZSTRIDE_1);
          assert(!(dst->origin & 0xf));
 
-         dw1_region = BRW_ADDRESS_DIRECT << 15 |
+         dw1_region = GEN6_ADDRMODE_DIRECT << 15 |
                       dst->horz_stride << 13 |
                       dst->origin |
                       dst->writemask;
@@ -282,7 +282,7 @@ translate_dst_region(const struct codegen *cg)
       else {
          assert(dst->writemask == TOY_WRITEMASK_XYZW);
 
-         dw1_region = BRW_ADDRESS_DIRECT << 15 |
+         dw1_region = GEN6_ADDRMODE_DIRECT << 15 |
                       dst->horz_stride << 13 |
                       dst->origin;
       }
@@ -368,15 +368,15 @@ codegen_inst_3src(const struct codegen *cg, uint32_t *code)
     *  - no regioning except replication control
     *    (vert_stride == 0 && horz_stride == 0)
     */
-   assert(cg->inst->access_mode == BRW_ALIGN_16);
+   assert(cg->inst->access_mode == GEN6_ALIGN_16);
 
    assert(!dst->indirect);
-   assert((dst->file == BRW_GENERAL_REGISTER_FILE &&
+   assert((dst->file == GEN6_FILE_GRF &&
            CG_REG_NUM(dst->origin) < 128) ||
-          (dst->file == BRW_MESSAGE_REGISTER_FILE &&
+          (dst->file == GEN6_FILE_MRF &&
            CG_REG_NUM(dst->origin) < 16));
    assert(!(dst->origin & 0x3));
-   assert(dst->horz_stride == BRW_HORIZONTAL_STRIDE_1);
+   assert(dst->horz_stride == GEN6_HORZSTRIDE_1);
 
    dw1 = dst->origin << 19 |
          dst->writemask << 17 |
@@ -387,29 +387,29 @@ codegen_inst_3src(const struct codegen *cg, uint32_t *code)
          cg->src[0].negate << 5 |
          cg->src[0].absolute << 4 |
          cg->flag_sub_reg_num << 1 |
-         (dst->file == BRW_MESSAGE_REGISTER_FILE);
+         (dst->file == GEN6_FILE_MRF);
 
    for (i = 0; i < 3; i++) {
       const struct codegen_src *src = &cg->src[i];
 
       assert(!src->indirect);
-      assert(src->file == BRW_GENERAL_REGISTER_FILE &&
+      assert(src->file == GEN6_FILE_GRF &&
              CG_REG_NUM(src->origin) < 128);
       assert(!(src->origin & 0x3));
 
-      assert((src->vert_stride == BRW_VERTICAL_STRIDE_4 &&
-              src->horz_stride == BRW_HORIZONTAL_STRIDE_1) ||
-             (src->vert_stride == BRW_VERTICAL_STRIDE_0 &&
-              src->horz_stride == BRW_HORIZONTAL_STRIDE_0));
-      assert(src->width == BRW_WIDTH_4);
+      assert((src->vert_stride == GEN6_VERTSTRIDE_4 &&
+              src->horz_stride == GEN6_HORZSTRIDE_1) ||
+             (src->vert_stride == GEN6_VERTSTRIDE_0 &&
+              src->horz_stride == GEN6_HORZSTRIDE_0));
+      assert(src->width == GEN6_WIDTH_4);
 
       dw_src[i] = src->origin << 7 |
                   src->swizzle[3] << 7 |
                   src->swizzle[2] << 5 |
                   src->swizzle[1] << 3 |
                   src->swizzle[0] << 1 |
-                  (src->vert_stride == BRW_VERTICAL_STRIDE_0 &&
-                   src->horz_stride == BRW_HORIZONTAL_STRIDE_0);
+                  (src->vert_stride == GEN6_VERTSTRIDE_0 &&
+                   src->horz_stride == GEN6_HORZSTRIDE_0);
 
       /* only the lower 20 bits are used */
       assert((dw_src[i] & 0xfffff) == dw_src[i]);
@@ -429,38 +429,38 @@ static void
 codegen_validate_region_restrictions(const struct codegen *cg)
 {
    const int exec_size_map[] = {
-      [BRW_EXECUTE_1] = 1,
-      [BRW_EXECUTE_2] = 2,
-      [BRW_EXECUTE_4] = 4,
-      [BRW_EXECUTE_8] = 8,
-      [BRW_EXECUTE_16] = 16,
-      [BRW_EXECUTE_32] = 32,
+      [GEN6_EXECSIZE_1] = 1,
+      [GEN6_EXECSIZE_2] = 2,
+      [GEN6_EXECSIZE_4] = 4,
+      [GEN6_EXECSIZE_8] = 8,
+      [GEN6_EXECSIZE_16] = 16,
+      [GEN6_EXECSIZE_32] = 32,
    };
    const int width_map[] = {
-      [BRW_WIDTH_1] = 1,
-      [BRW_WIDTH_2] = 2,
-      [BRW_WIDTH_4] = 4,
-      [BRW_WIDTH_8] = 8,
-      [BRW_WIDTH_16] = 16,
+      [GEN6_WIDTH_1] = 1,
+      [GEN6_WIDTH_2] = 2,
+      [GEN6_WIDTH_4] = 4,
+      [GEN6_WIDTH_8] = 8,
+      [GEN6_WIDTH_16] = 16,
    };
    const int horz_stride_map[] = {
-      [BRW_HORIZONTAL_STRIDE_0] = 0,
-      [BRW_HORIZONTAL_STRIDE_1] = 1,
-      [BRW_HORIZONTAL_STRIDE_2] = 2,
-      [BRW_HORIZONTAL_STRIDE_4] = 4,
+      [GEN6_HORZSTRIDE_0] = 0,
+      [GEN6_HORZSTRIDE_1] = 1,
+      [GEN6_HORZSTRIDE_2] = 2,
+      [GEN6_HORZSTRIDE_4] = 4,
    };
    const int vert_stride_map[] = {
-      [BRW_VERTICAL_STRIDE_0] = 0,
-      [BRW_VERTICAL_STRIDE_1] = 1,
-      [BRW_VERTICAL_STRIDE_2] = 2,
-      [BRW_VERTICAL_STRIDE_4] = 4,
-      [BRW_VERTICAL_STRIDE_8] = 8,
-      [BRW_VERTICAL_STRIDE_16] = 16,
-      [BRW_VERTICAL_STRIDE_32] = 32,
-      [BRW_VERTICAL_STRIDE_64] = 64,
-      [BRW_VERTICAL_STRIDE_128] = 128,
-      [BRW_VERTICAL_STRIDE_256] = 256,
-      [BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL] = 0,
+      [GEN6_VERTSTRIDE_0] = 0,
+      [GEN6_VERTSTRIDE_1] = 1,
+      [GEN6_VERTSTRIDE_2] = 2,
+      [GEN6_VERTSTRIDE_4] = 4,
+      [GEN6_VERTSTRIDE_8] = 8,
+      [GEN6_VERTSTRIDE_16] = 16,
+      [GEN6_VERTSTRIDE_32] = 32,
+      [7] = 64,
+      [8] = 128,
+      [9] = 256,
+      [GEN6_VERTSTRIDE_VXH] = 0,
    };
    const int exec_size = exec_size_map[cg->inst->exec_size];
    int i;
@@ -502,20 +502,20 @@ codegen_validate_region_restrictions(const struct codegen *cg)
    }
 
    /* derived from 10.1.2. & 10.2. */
-   assert(cg->dst.horz_stride != BRW_HORIZONTAL_STRIDE_0);
+   assert(cg->dst.horz_stride != GEN6_HORZSTRIDE_0);
 }
 
 static unsigned
 translate_vfile(enum toy_file file)
 {
    switch (file) {
-   case TOY_FILE_ARF:   return BRW_ARCHITECTURE_REGISTER_FILE;
-   case TOY_FILE_GRF:   return BRW_GENERAL_REGISTER_FILE;
-   case TOY_FILE_MRF:   return BRW_MESSAGE_REGISTER_FILE;
-   case TOY_FILE_IMM:   return BRW_IMMEDIATE_VALUE;
+   case TOY_FILE_ARF:   return GEN6_FILE_ARF;
+   case TOY_FILE_GRF:   return GEN6_FILE_GRF;
+   case TOY_FILE_MRF:   return GEN6_FILE_MRF;
+   case TOY_FILE_IMM:   return GEN6_FILE_IMM;
    default:
       assert(!"unhandled toy file");
-      return BRW_GENERAL_REGISTER_FILE;
+      return GEN6_FILE_GRF;
    }
 }
 
@@ -523,15 +523,15 @@ static unsigned
 translate_vtype(enum toy_type type)
 {
    switch (type) {
-   case TOY_TYPE_F:     return BRW_REGISTER_TYPE_F;
-   case TOY_TYPE_D:     return BRW_REGISTER_TYPE_D;
-   case TOY_TYPE_UD:    return BRW_REGISTER_TYPE_UD;
-   case TOY_TYPE_W:     return BRW_REGISTER_TYPE_W;
-   case TOY_TYPE_UW:    return BRW_REGISTER_TYPE_UW;
-   case TOY_TYPE_V:     return BRW_REGISTER_TYPE_V;
+   case TOY_TYPE_F:     return GEN6_TYPE_F;
+   case TOY_TYPE_D:     return GEN6_TYPE_D;
+   case TOY_TYPE_UD:    return GEN6_TYPE_UD;
+   case TOY_TYPE_W:     return GEN6_TYPE_W;
+   case TOY_TYPE_UW:    return GEN6_TYPE_UW;
+   case TOY_TYPE_V:     return GEN6_TYPE_V_IMM;
    default:
       assert(!"unhandled toy type");
-      return BRW_REGISTER_TYPE_F;
+      return GEN6_TYPE_F;
    }
 }
 
@@ -594,11 +594,11 @@ codegen_prepare(struct codegen *cg, const struct toy_inst *inst,
 
    switch (inst->dst.rect) {
    case TOY_RECT_LINEAR:
-      cg->dst.horz_stride = BRW_HORIZONTAL_STRIDE_1;
+      cg->dst.horz_stride = GEN6_HORZSTRIDE_1;
       break;
    default:
       assert(!"unsupported dst region");
-      cg->dst.horz_stride = BRW_HORIZONTAL_STRIDE_1;
+      cg->dst.horz_stride = GEN6_HORZSTRIDE_1;
       break;
    }
 
@@ -635,63 +635,63 @@ codegen_prepare(struct codegen *cg, const struct toy_inst *inst,
       case TOY_RECT_LINEAR:
          switch (rect_linear_width) {
          case 1:
-            src->vert_stride = BRW_VERTICAL_STRIDE_1;
-            src->width = BRW_WIDTH_1;
+            src->vert_stride = GEN6_VERTSTRIDE_1;
+            src->width = GEN6_WIDTH_1;
             break;
          case 2:
-            src->vert_stride = BRW_VERTICAL_STRIDE_2;
-            src->width = BRW_WIDTH_2;
+            src->vert_stride = GEN6_VERTSTRIDE_2;
+            src->width = GEN6_WIDTH_2;
             break;
          case 4:
-            src->vert_stride = BRW_VERTICAL_STRIDE_4;
-            src->width = BRW_WIDTH_4;
+            src->vert_stride = GEN6_VERTSTRIDE_4;
+            src->width = GEN6_WIDTH_4;
             break;
          case 8:
-            src->vert_stride = BRW_VERTICAL_STRIDE_8;
-            src->width = BRW_WIDTH_8;
+            src->vert_stride = GEN6_VERTSTRIDE_8;
+            src->width = GEN6_WIDTH_8;
             break;
          case 16:
-            src->vert_stride = BRW_VERTICAL_STRIDE_16;
-            src->width = BRW_WIDTH_16;
+            src->vert_stride = GEN6_VERTSTRIDE_16;
+            src->width = GEN6_WIDTH_16;
             break;
          default:
             assert(!"unsupported TOY_RECT_LINEAR width");
-            src->vert_stride = BRW_VERTICAL_STRIDE_1;
-            src->width = BRW_WIDTH_1;
+            src->vert_stride = GEN6_VERTSTRIDE_1;
+            src->width = GEN6_WIDTH_1;
             break;
          }
-         src->horz_stride = BRW_HORIZONTAL_STRIDE_1;
+         src->horz_stride = GEN6_HORZSTRIDE_1;
          break;
       case TOY_RECT_041:
-         src->vert_stride = BRW_VERTICAL_STRIDE_0;
-         src->width = BRW_WIDTH_4;
-         src->horz_stride = BRW_HORIZONTAL_STRIDE_1;
+         src->vert_stride = GEN6_VERTSTRIDE_0;
+         src->width = GEN6_WIDTH_4;
+         src->horz_stride = GEN6_HORZSTRIDE_1;
          break;
       case TOY_RECT_010:
-         src->vert_stride = BRW_VERTICAL_STRIDE_0;
-         src->width = BRW_WIDTH_1;
-         src->horz_stride = BRW_HORIZONTAL_STRIDE_0;
+         src->vert_stride = GEN6_VERTSTRIDE_0;
+         src->width = GEN6_WIDTH_1;
+         src->horz_stride = GEN6_HORZSTRIDE_0;
          break;
       case TOY_RECT_220:
-         src->vert_stride = BRW_VERTICAL_STRIDE_2;
-         src->width = BRW_WIDTH_2;
-         src->horz_stride = BRW_HORIZONTAL_STRIDE_0;
+         src->vert_stride = GEN6_VERTSTRIDE_2;
+         src->width = GEN6_WIDTH_2;
+         src->horz_stride = GEN6_HORZSTRIDE_0;
          break;
       case TOY_RECT_440:
-         src->vert_stride = BRW_VERTICAL_STRIDE_4;
-         src->width = BRW_WIDTH_4;
-         src->horz_stride = BRW_HORIZONTAL_STRIDE_0;
+         src->vert_stride = GEN6_VERTSTRIDE_4;
+         src->width = GEN6_WIDTH_4;
+         src->horz_stride = GEN6_HORZSTRIDE_0;
          break;
       case TOY_RECT_240:
-         src->vert_stride = BRW_VERTICAL_STRIDE_2;
-         src->width = BRW_WIDTH_4;
-         src->horz_stride = BRW_HORIZONTAL_STRIDE_0;
+         src->vert_stride = GEN6_VERTSTRIDE_2;
+         src->width = GEN6_WIDTH_4;
+         src->horz_stride = GEN6_HORZSTRIDE_0;
          break;
       default:
          assert(!"unsupported src region");
-         src->vert_stride = BRW_VERTICAL_STRIDE_1;
-         src->width = BRW_WIDTH_1;
-         src->horz_stride = BRW_HORIZONTAL_STRIDE_1;
+         src->vert_stride = GEN6_VERTSTRIDE_1;
+         src->width = GEN6_WIDTH_1;
+         src->horz_stride = GEN6_HORZSTRIDE_1;
          break;
       }
    }
@@ -726,7 +726,7 @@ toy_compiler_assemble(struct toy_compiler *tc, int *size)
       codegen_validate_region_restrictions(&cg);
 
       switch (inst->opcode) {
-      case BRW_OPCODE_MAD:
+      case GEN6_OPCODE_MAD:
          codegen_inst_3src(&cg, dw);
          break;
       default:
diff --git a/src/gallium/drivers/ilo/shader/toy_compiler_reg.h b/src/gallium/drivers/ilo/shader/toy_compiler_reg.h
index 8c11b3a..36674f8 100644
--- a/src/gallium/drivers/ilo/shader/toy_compiler_reg.h
+++ b/src/gallium/drivers/ilo/shader/toy_compiler_reg.h
@@ -213,7 +213,7 @@ toy_type_size(enum toy_type type)
 static inline bool
 tdst_is_null(struct toy_dst dst)
 {
-   /* BRW_ARF_NULL happens to be 0 */
+   /* GEN6_ARF_NULL happens to be 0 */
    return (dst.file == TOY_FILE_ARF && dst.val32 == 0);
 }
 
@@ -431,7 +431,7 @@ tdst_imm_w(int16_t w)
 static inline bool
 tsrc_is_null(struct toy_src src)
 {
-   /* BRW_ARF_NULL happens to be 0 */
+   /* GEN6_ARF_NULL happens to be 0 */
    return (src.file == TOY_FILE_ARF && src.val32 == 0);
 }
 
diff --git a/src/gallium/drivers/ilo/shader/toy_helpers.h b/src/gallium/drivers/ilo/shader/toy_helpers.h
index 038a81f..2e96ef8 100644
--- a/src/gallium/drivers/ilo/shader/toy_helpers.h
+++ b/src/gallium/drivers/ilo/shader/toy_helpers.h
@@ -208,7 +208,7 @@ tsrc_imm_mdesc_data_port(const struct toy_compiler *tc,
    }
    else {
       assert(!send_write_commit_message ||
-             message_type == GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE);
+             message_type == GEN6_MSG_DP_SVB_WRITE);
       assert((message_specific_control & 0x1f00) == message_specific_control);
 
       ctrl = send_write_commit_message << 17 |
diff --git a/src/gallium/drivers/ilo/shader/toy_legalize.c b/src/gallium/drivers/ilo/shader/toy_legalize.c
index 2339b7d..d632a57 100644
--- a/src/gallium/drivers/ilo/shader/toy_legalize.c
+++ b/src/gallium/drivers/ilo/shader/toy_legalize.c
@@ -32,7 +32,7 @@
 #include "toy_legalize.h"
 
 /**
- * Lower an instruction to BRW_OPCODE_SEND(C).
+ * Lower an instruction to GEN6_OPCODE_SEND(C).
  */
 void
 toy_compiler_lower_to_send(struct toy_compiler *tc, struct toy_inst *inst,
@@ -40,12 +40,12 @@ toy_compiler_lower_to_send(struct toy_compiler *tc, struct toy_inst *inst,
 {
    assert(inst->opcode >= 128);
 
-   inst->opcode = (sendc) ? BRW_OPCODE_SENDC : BRW_OPCODE_SEND;
+   inst->opcode = (sendc) ? GEN6_OPCODE_SENDC : GEN6_OPCODE_SEND;
 
    /* thread control is reserved */
    assert(inst->thread_ctrl == 0);
 
-   assert(inst->cond_modifier == BRW_CONDITIONAL_NONE);
+   assert(inst->cond_modifier == GEN6_COND_NORMAL);
    inst->cond_modifier = sfid;
 }
 
@@ -53,17 +53,17 @@ static int
 math_op_to_func(unsigned opcode)
 {
    switch (opcode) {
-   case TOY_OPCODE_INV:    return BRW_MATH_FUNCTION_INV;
-   case TOY_OPCODE_LOG:    return BRW_MATH_FUNCTION_LOG;
-   case TOY_OPCODE_EXP:    return BRW_MATH_FUNCTION_EXP;
-   case TOY_OPCODE_SQRT:   return BRW_MATH_FUNCTION_SQRT;
-   case TOY_OPCODE_RSQ:    return BRW_MATH_FUNCTION_RSQ;
-   case TOY_OPCODE_SIN:    return BRW_MATH_FUNCTION_SIN;
-   case TOY_OPCODE_COS:    return BRW_MATH_FUNCTION_COS;
-   case TOY_OPCODE_FDIV:   return BRW_MATH_FUNCTION_FDIV;
-   case TOY_OPCODE_POW:    return BRW_MATH_FUNCTION_POW;
-   case TOY_OPCODE_INT_DIV_QUOTIENT:   return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
-   case TOY_OPCODE_INT_DIV_REMAINDER:  return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
+   case TOY_OPCODE_INV:    return GEN6_MATH_INV;
+   case TOY_OPCODE_LOG:    return GEN6_MATH_LOG;
+   case TOY_OPCODE_EXP:    return GEN6_MATH_EXP;
+   case TOY_OPCODE_SQRT:   return GEN6_MATH_SQRT;
+   case TOY_OPCODE_RSQ:    return GEN6_MATH_RSQ;
+   case TOY_OPCODE_SIN:    return GEN6_MATH_SIN;
+   case TOY_OPCODE_COS:    return GEN6_MATH_COS;
+   case TOY_OPCODE_FDIV:   return GEN6_MATH_FDIV;
+   case TOY_OPCODE_POW:    return GEN6_MATH_POW;
+   case TOY_OPCODE_INT_DIV_QUOTIENT:   return GEN6_MATH_INT_DIV_QUOTIENT;
+   case TOY_OPCODE_INT_DIV_REMAINDER:  return GEN6_MATH_INT_DIV_REMAINDER;
    default:
        assert(!"unknown math opcode");
        return -1;
@@ -71,7 +71,7 @@ math_op_to_func(unsigned opcode)
 }
 
 /**
- * Lower virtual math opcodes to BRW_OPCODE_MATH.
+ * Lower virtual math opcodes to GEN6_OPCODE_MATH.
  */
 void
 toy_compiler_lower_math(struct toy_compiler *tc, struct toy_inst *inst)
@@ -98,13 +98,13 @@ toy_compiler_lower_math(struct toy_compiler *tc, struct toy_inst *inst)
    }
 
    /* FC[0:3] */
-   assert(inst->cond_modifier == BRW_CONDITIONAL_NONE);
+   assert(inst->cond_modifier == GEN6_COND_NORMAL);
    inst->cond_modifier = math_op_to_func(inst->opcode);
    /* FC[4:5] */
    assert(inst->thread_ctrl == 0);
    inst->thread_ctrl = 0;
 
-   inst->opcode = BRW_OPCODE_MATH;
+   inst->opcode = GEN6_OPCODE_MATH;
    tc_move_inst(tc, inst);
 
    /* no writemask in align1 */
@@ -223,7 +223,7 @@ lower_opcode_mul(struct toy_compiler *tc, struct toy_inst *inst)
 {
    const enum toy_type inst_type = inst->dst.type;
    const struct toy_dst acc0 =
-      tdst_type(tdst(TOY_FILE_ARF, BRW_ARF_ACCUMULATOR, 0), inst_type);
+      tdst_type(tdst(TOY_FILE_ARF, GEN6_ARF_ACC0, 0), inst_type);
    struct toy_inst *inst2;
 
    /* only need to take care of integer multiplications */
@@ -234,7 +234,7 @@ lower_opcode_mul(struct toy_compiler *tc, struct toy_inst *inst)
    tc_MUL(tc, acc0, inst->src[0], inst->src[1]);
 
    /* acc0 = (src0 & 0xffff0000) * src1 + acc0 */
-   inst2 = tc_add2(tc, BRW_OPCODE_MACH, tdst_type(tdst_null(), inst_type),
+   inst2 = tc_add2(tc, GEN6_OPCODE_MACH, tdst_type(tdst_null(), inst_type),
          inst->src[0], inst->src[1]);
    inst2->acc_wr_ctrl = true;
 
@@ -250,7 +250,7 @@ lower_opcode_mac(struct toy_compiler *tc, struct toy_inst *inst)
    const enum toy_type inst_type = inst->dst.type;
 
    if (inst_type != TOY_TYPE_UD && inst_type != TOY_TYPE_D) {
-      const struct toy_dst acc0 = tdst(TOY_FILE_ARF, BRW_ARF_ACCUMULATOR, 0);
+      const struct toy_dst acc0 = tdst(TOY_FILE_ARF, GEN6_ARF_ACC0, 0);
 
       tc_MOV(tc, acc0, inst->src[2]);
       inst->src[2] = tsrc_null();
@@ -280,13 +280,13 @@ toy_compiler_legalize_for_ra(struct toy_compiler *tc)
    tc_head(tc);
    while ((inst = tc_next(tc)) != NULL) {
       switch (inst->opcode) {
-      case BRW_OPCODE_MAC:
+      case GEN6_OPCODE_MAC:
          lower_opcode_mac(tc, inst);
          break;
-      case BRW_OPCODE_MAD:
+      case GEN6_OPCODE_MAD:
          /* TODO operands must be floats */
          break;
-      case BRW_OPCODE_MUL:
+      case GEN6_OPCODE_MUL:
          lower_opcode_mul(tc, inst);
          break;
       default:
@@ -329,7 +329,7 @@ patch_while_jip(struct toy_compiler *tc, struct toy_inst *inst)
          continue;
       }
 
-      if (inst2->opcode == BRW_OPCODE_WHILE)
+      if (inst2->opcode == GEN6_OPCODE_WHILE)
          nest_level++;
 
       dist--;
@@ -358,7 +358,7 @@ patch_if_else_jip(struct toy_compiler *tc, struct toy_inst *inst)
       if (inst2->marker)
          continue;
 
-      if (inst2->opcode == BRW_OPCODE_ENDIF) {
+      if (inst2->opcode == GEN6_OPCODE_ENDIF) {
          if (nest_level) {
             nest_level--;
          }
@@ -369,8 +369,8 @@ patch_if_else_jip(struct toy_compiler *tc, struct toy_inst *inst)
             break;
          }
       }
-      else if (inst2->opcode == BRW_OPCODE_ELSE &&
-               inst->opcode == BRW_OPCODE_IF) {
+      else if (inst2->opcode == GEN6_OPCODE_ELSE &&
+               inst->opcode == GEN6_OPCODE_IF) {
          if (!nest_level) {
             /* the following instruction */
             jip = (dist + 1) * 2;
@@ -381,7 +381,7 @@ patch_if_else_jip(struct toy_compiler *tc, struct toy_inst *inst)
             }
          }
       }
-      else if (inst2->opcode == BRW_OPCODE_IF) {
+      else if (inst2->opcode == GEN6_OPCODE_IF) {
          nest_level++;
       }
 
@@ -398,7 +398,7 @@ patch_if_else_jip(struct toy_compiler *tc, struct toy_inst *inst)
       inst->dst = tdst_imm_w(jip);
    }
 
-   inst->thread_ctrl = BRW_THREAD_SWITCH;
+   inst->thread_ctrl = GEN6_THREADCTRL_SWITCH;
 }
 
 static void
@@ -414,9 +414,9 @@ patch_endif_jip(struct toy_compiler *tc, struct toy_inst *inst)
          continue;
 
       switch (inst2->opcode) {
-      case BRW_OPCODE_ENDIF:
-      case BRW_OPCODE_ELSE:
-      case BRW_OPCODE_WHILE:
+      case GEN6_OPCODE_ENDIF:
+      case GEN6_OPCODE_ELSE:
+      case GEN6_OPCODE_WHILE:
          found = true;
          break;
       default:
@@ -438,7 +438,7 @@ patch_endif_jip(struct toy_compiler *tc, struct toy_inst *inst)
    else
       inst->dst = tdst_imm_w(dist * 2);
 
-   inst->thread_ctrl = BRW_THREAD_SWITCH;
+   inst->thread_ctrl = GEN6_THREADCTRL_SWITCH;
 }
 
 static void
@@ -460,9 +460,9 @@ patch_break_continue_jip(struct toy_compiler *tc, struct toy_inst *inst)
          continue;
       }
 
-      if (inst2->opcode == BRW_OPCODE_ELSE ||
-          inst2->opcode == BRW_OPCODE_ENDIF ||
-          inst2->opcode == BRW_OPCODE_WHILE) {
+      if (inst2->opcode == GEN6_OPCODE_ELSE ||
+          inst2->opcode == GEN6_OPCODE_ENDIF ||
+          inst2->opcode == GEN6_OPCODE_WHILE) {
          jip = dist * 2;
          break;
       }
@@ -479,13 +479,13 @@ patch_break_continue_jip(struct toy_compiler *tc, struct toy_inst *inst)
          continue;
       }
 
-      if (inst2->opcode == BRW_OPCODE_WHILE) {
+      if (inst2->opcode == GEN6_OPCODE_WHILE) {
          if (nest_level) {
             nest_level--;
          }
          else {
             /* the following instruction */
-            if (tc->dev->gen == ILO_GEN(6) && inst->opcode == BRW_OPCODE_BREAK)
+            if (tc->dev->gen == ILO_GEN(6) && inst->opcode == GEN6_OPCODE_BREAK)
                dist++;
 
             uip = dist * 2;
@@ -536,26 +536,26 @@ toy_compiler_legalize_for_asm(struct toy_compiler *tc)
          inst->src[1].type = inst->src[0].type;
 
       switch (inst->opcode) {
-      case BRW_OPCODE_MATH:
+      case GEN6_OPCODE_MATH:
          /* math does not support align16 nor exec_size > 8 */
-         inst->access_mode = BRW_ALIGN_1;
+         inst->access_mode = GEN6_ALIGN_1;
 
-         if (inst->exec_size == BRW_EXECUTE_16) {
+         if (inst->exec_size == GEN6_EXECSIZE_16) {
             /*
              * From the Ivy Bridge PRM, volume 4 part 3, page 192:
              *
              *     "INT DIV function does not support SIMD16."
              */
             if (tc->dev->gen < ILO_GEN(7) ||
-                inst->cond_modifier == BRW_MATH_FUNCTION_INT_DIV_QUOTIENT ||
-                inst->cond_modifier == BRW_MATH_FUNCTION_INT_DIV_REMAINDER) {
+                inst->cond_modifier == GEN6_MATH_INT_DIV_QUOTIENT ||
+                inst->cond_modifier == GEN6_MATH_INT_DIV_REMAINDER) {
                struct toy_inst *inst2;
 
-               inst->exec_size = BRW_EXECUTE_8;
-               inst->qtr_ctrl = GEN6_COMPRESSION_1Q;
+               inst->exec_size = GEN6_EXECSIZE_8;
+               inst->qtr_ctrl = GEN6_QTRCTRL_1Q;
 
                inst2 = tc_duplicate_inst(tc, inst);
-               inst2->qtr_ctrl = GEN6_COMPRESSION_2Q;
+               inst2->qtr_ctrl = GEN6_QTRCTRL_2Q;
                inst2->dst = tdst_offset(inst2->dst, 1, 0);
                inst2->src[0] = tsrc_offset(inst2->src[0], 1, 0);
                if (!tsrc_is_null(inst2->src[1]))
@@ -565,22 +565,22 @@ toy_compiler_legalize_for_asm(struct toy_compiler *tc)
             }
          }
          break;
-      case BRW_OPCODE_IF:
+      case GEN6_OPCODE_IF:
          if (tc->dev->gen >= ILO_GEN(7) &&
-             inst->cond_modifier != BRW_CONDITIONAL_NONE) {
+             inst->cond_modifier != GEN6_COND_NORMAL) {
             struct toy_inst *inst2;
 
             inst2 = tc_duplicate_inst(tc, inst);
 
             /* replace the original IF by CMP */
-            inst->opcode = BRW_OPCODE_CMP;
+            inst->opcode = GEN6_OPCODE_CMP;
 
             /* predicate control instead of condition modifier */
             inst2->dst = tdst_null();
             inst2->src[0] = tsrc_null();
             inst2->src[1] = tsrc_null();
-            inst2->cond_modifier = BRW_CONDITIONAL_NONE;
-            inst2->pred_ctrl = BRW_PREDICATE_NORMAL;
+            inst2->cond_modifier = GEN6_COND_NORMAL;
+            inst2->pred_ctrl = GEN6_PREDCTRL_NORMAL;
 
             pc++;
          }
@@ -611,18 +611,18 @@ toy_compiler_legalize_for_asm(struct toy_compiler *tc)
    tc_head(tc);
    while ((inst = tc_next(tc)) != NULL) {
       switch (inst->opcode) {
-      case BRW_OPCODE_IF:
-      case BRW_OPCODE_ELSE:
+      case GEN6_OPCODE_IF:
+      case GEN6_OPCODE_ELSE:
          patch_if_else_jip(tc, inst);
          break;
-      case BRW_OPCODE_ENDIF:
+      case GEN6_OPCODE_ENDIF:
          patch_endif_jip(tc, inst);
          break;
-      case BRW_OPCODE_WHILE:
+      case GEN6_OPCODE_WHILE:
          patch_while_jip(tc, inst);
          break;
-      case BRW_OPCODE_BREAK:
-      case BRW_OPCODE_CONTINUE:
+      case GEN6_OPCODE_BREAK:
+      case GEN6_OPCODE_CONT:
          patch_break_continue_jip(tc, inst);
          break;
       default:
diff --git a/src/gallium/drivers/ilo/shader/toy_legalize_ra.c b/src/gallium/drivers/ilo/shader/toy_legalize_ra.c
index ba05b0a..b725375 100644
--- a/src/gallium/drivers/ilo/shader/toy_legalize_ra.c
+++ b/src/gallium/drivers/ilo/shader/toy_legalize_ra.c
@@ -244,7 +244,7 @@ linear_scan_run(struct linear_scan *ls)
       int reg, count;
 
       /*
-       * BRW_OPCODE_SEND may write to multiple consecutive registers and we need to
+       * GEN6_OPCODE_SEND may write to multiple consecutive registers and we need to
        * support that
        */
       for (count = 1; i + count < ls->num_vrfs; count++) {
@@ -355,7 +355,7 @@ linear_scan_init_live_intervals(struct linear_scan *ls,
             do_pc = pc;
             while_pc = pc + 1;
 
-            /* find the matching BRW_OPCODE_WHILE */
+            /* find the matching GEN6_OPCODE_WHILE */
             LIST_FOR_EACH_ENTRY_FROM(inst2, tc->iter_next,
                   &tc->instructions, list) {
                if (inst2->marker) {
@@ -364,7 +364,7 @@ linear_scan_init_live_intervals(struct linear_scan *ls,
                   continue;
                }
 
-               if (inst2->opcode == BRW_OPCODE_WHILE) {
+               if (inst2->opcode == GEN6_OPCODE_WHILE) {
                   loop_level--;
                   if (!loop_level)
                      break;
@@ -380,13 +380,13 @@ linear_scan_init_live_intervals(struct linear_scan *ls,
          int num_dst;
 
          /* TODO this is a hack */
-         if (inst->opcode == BRW_OPCODE_SEND ||
-             inst->opcode == BRW_OPCODE_SENDC) {
+         if (inst->opcode == GEN6_OPCODE_SEND ||
+             inst->opcode == GEN6_OPCODE_SENDC) {
             const uint32_t mdesc = inst->src[1].val32;
             int response_length = (mdesc >> 20) & 0x1f;
 
             num_dst = response_length;
-            if (num_dst > 1 && inst->exec_size == BRW_EXECUTE_16)
+            if (num_dst > 1 && inst->exec_size == GEN6_EXECSIZE_16)
                num_dst /= 2;
          }
          else {
diff --git a/src/gallium/drivers/ilo/shader/toy_optimize.c b/src/gallium/drivers/ilo/shader/toy_optimize.c
index 62a663f..97a04c8 100644
--- a/src/gallium/drivers/ilo/shader/toy_optimize.c
+++ b/src/gallium/drivers/ilo/shader/toy_optimize.c
@@ -40,22 +40,22 @@ eliminate_dead_code(struct toy_compiler *tc)
    tc_head(tc);
    while ((inst = tc_next(tc)) != NULL) {
       switch (inst->opcode) {
-      case BRW_OPCODE_IF:
-      case BRW_OPCODE_ELSE:
-      case BRW_OPCODE_ENDIF:
-      case BRW_OPCODE_WHILE:
-      case BRW_OPCODE_BREAK:
-      case BRW_OPCODE_CONTINUE:
-      case BRW_OPCODE_SEND:
-      case BRW_OPCODE_SENDC:
-      case BRW_OPCODE_NOP:
+      case GEN6_OPCODE_IF:
+      case GEN6_OPCODE_ELSE:
+      case GEN6_OPCODE_ENDIF:
+      case GEN6_OPCODE_WHILE:
+      case GEN6_OPCODE_BREAK:
+      case GEN6_OPCODE_CONT:
+      case GEN6_OPCODE_SEND:
+      case GEN6_OPCODE_SENDC:
+      case GEN6_OPCODE_NOP:
          /* never eliminated */
          break;
       default:
          if (tdst_is_null(inst->dst) || !inst->dst.writemask) {
-            /* math is always BRW_CONDITIONAL_NONE */
-            if ((inst->opcode == BRW_OPCODE_MATH ||
-                 inst->cond_modifier == BRW_CONDITIONAL_NONE) &&
+            /* math is always GEN6_COND_NORMAL */
+            if ((inst->opcode == GEN6_OPCODE_MATH ||
+                 inst->cond_modifier == GEN6_COND_NORMAL) &&
                 !inst->acc_wr_ctrl)
                tc_discard_inst(tc, inst);
          }
diff --git a/src/gallium/drivers/ilo/shader/toy_tgsi.c b/src/gallium/drivers/ilo/shader/toy_tgsi.c
index a0db732..e816ab4 100644
--- a/src/gallium/drivers/ilo/shader/toy_tgsi.c
+++ b/src/gallium/drivers/ilo/shader/toy_tgsi.c
@@ -38,69 +38,69 @@ static const struct {
    int num_dst;
    int num_src;
 } aos_simple_opcode_map[TGSI_OPCODE_LAST] = {
-   [TGSI_OPCODE_ARL]          = { BRW_OPCODE_RNDD,                1, 1 },
-   [TGSI_OPCODE_MOV]          = { BRW_OPCODE_MOV,                 1, 1 },
+   [TGSI_OPCODE_ARL]          = { GEN6_OPCODE_RNDD,                1, 1 },
+   [TGSI_OPCODE_MOV]          = { GEN6_OPCODE_MOV,                 1, 1 },
    [TGSI_OPCODE_RCP]          = { TOY_OPCODE_INV,                 1, 1 },
    [TGSI_OPCODE_RSQ]          = { TOY_OPCODE_RSQ,                 1, 1 },
-   [TGSI_OPCODE_MUL]          = { BRW_OPCODE_MUL,                 1, 2 },
-   [TGSI_OPCODE_ADD]          = { BRW_OPCODE_ADD,                 1, 2 },
-   [TGSI_OPCODE_DP3]          = { BRW_OPCODE_DP3,                 1, 2 },
-   [TGSI_OPCODE_DP4]          = { BRW_OPCODE_DP4,                 1, 2 },
-   [TGSI_OPCODE_MIN]          = { BRW_OPCODE_SEL,                 1, 2 },
-   [TGSI_OPCODE_MAX]          = { BRW_OPCODE_SEL,                 1, 2 },
+   [TGSI_OPCODE_MUL]          = { GEN6_OPCODE_MUL,                 1, 2 },
+   [TGSI_OPCODE_ADD]          = { GEN6_OPCODE_ADD,                 1, 2 },
+   [TGSI_OPCODE_DP3]          = { GEN6_OPCODE_DP3,                 1, 2 },
+   [TGSI_OPCODE_DP4]          = { GEN6_OPCODE_DP4,                 1, 2 },
+   [TGSI_OPCODE_MIN]          = { GEN6_OPCODE_SEL,                 1, 2 },
+   [TGSI_OPCODE_MAX]          = { GEN6_OPCODE_SEL,                 1, 2 },
    /* a later pass will move src[2] to accumulator */
-   [TGSI_OPCODE_MAD]          = { BRW_OPCODE_MAC,                 1, 3 },
-   [TGSI_OPCODE_SUB]          = { BRW_OPCODE_ADD,                 1, 2 },
+   [TGSI_OPCODE_MAD]          = { GEN6_OPCODE_MAC,                 1, 3 },
+   [TGSI_OPCODE_SUB]          = { GEN6_OPCODE_ADD,                 1, 2 },
    [TGSI_OPCODE_SQRT]         = { TOY_OPCODE_SQRT,                1, 1 },
-   [TGSI_OPCODE_FRC]          = { BRW_OPCODE_FRC,                 1, 1 },
-   [TGSI_OPCODE_FLR]          = { BRW_OPCODE_RNDD,                1, 1 },
-   [TGSI_OPCODE_ROUND]        = { BRW_OPCODE_RNDE,                1, 1 },
+   [TGSI_OPCODE_FRC]          = { GEN6_OPCODE_FRC,                 1, 1 },
+   [TGSI_OPCODE_FLR]          = { GEN6_OPCODE_RNDD,                1, 1 },
+   [TGSI_OPCODE_ROUND]        = { GEN6_OPCODE_RNDE,                1, 1 },
    [TGSI_OPCODE_EX2]          = { TOY_OPCODE_EXP,                 1, 1 },
    [TGSI_OPCODE_LG2]          = { TOY_OPCODE_LOG,                 1, 1 },
    [TGSI_OPCODE_POW]          = { TOY_OPCODE_POW,                 1, 2 },
-   [TGSI_OPCODE_ABS]          = { BRW_OPCODE_MOV,                 1, 1 },
-   [TGSI_OPCODE_DPH]          = { BRW_OPCODE_DPH,                 1, 2 },
+   [TGSI_OPCODE_ABS]          = { GEN6_OPCODE_MOV,                 1, 1 },
+   [TGSI_OPCODE_DPH]          = { GEN6_OPCODE_DPH,                 1, 2 },
    [TGSI_OPCODE_COS]          = { TOY_OPCODE_COS,                 1, 1 },
    [TGSI_OPCODE_KILL]         = { TOY_OPCODE_KIL,                 0, 0 },
    [TGSI_OPCODE_SIN]          = { TOY_OPCODE_SIN,                 1, 1 },
-   [TGSI_OPCODE_ARR]          = { BRW_OPCODE_RNDZ,                1, 1 },
-   [TGSI_OPCODE_DP2]          = { BRW_OPCODE_DP2,                 1, 2 },
-   [TGSI_OPCODE_IF]           = { BRW_OPCODE_IF,                  0, 1 },
-   [TGSI_OPCODE_UIF]          = { BRW_OPCODE_IF,                  0, 1 },
-   [TGSI_OPCODE_ELSE]         = { BRW_OPCODE_ELSE,                0, 0 },
-   [TGSI_OPCODE_ENDIF]        = { BRW_OPCODE_ENDIF,               0, 0 },
-   [TGSI_OPCODE_I2F]          = { BRW_OPCODE_MOV,                 1, 1 },
-   [TGSI_OPCODE_NOT]          = { BRW_OPCODE_NOT,                 1, 1 },
-   [TGSI_OPCODE_TRUNC]        = { BRW_OPCODE_RNDZ,                1, 1 },
-   [TGSI_OPCODE_SHL]          = { BRW_OPCODE_SHL,                 1, 2 },
-   [TGSI_OPCODE_AND]          = { BRW_OPCODE_AND,                 1, 2 },
-   [TGSI_OPCODE_OR]           = { BRW_OPCODE_OR,                  1, 2 },
+   [TGSI_OPCODE_ARR]          = { GEN6_OPCODE_RNDZ,                1, 1 },
+   [TGSI_OPCODE_DP2]          = { GEN6_OPCODE_DP2,                 1, 2 },
+   [TGSI_OPCODE_IF]           = { GEN6_OPCODE_IF,                  0, 1 },
+   [TGSI_OPCODE_UIF]          = { GEN6_OPCODE_IF,                  0, 1 },
+   [TGSI_OPCODE_ELSE]         = { GEN6_OPCODE_ELSE,                0, 0 },
+   [TGSI_OPCODE_ENDIF]        = { GEN6_OPCODE_ENDIF,               0, 0 },
+   [TGSI_OPCODE_I2F]          = { GEN6_OPCODE_MOV,                 1, 1 },
+   [TGSI_OPCODE_NOT]          = { GEN6_OPCODE_NOT,                 1, 1 },
+   [TGSI_OPCODE_TRUNC]        = { GEN6_OPCODE_RNDZ,                1, 1 },
+   [TGSI_OPCODE_SHL]          = { GEN6_OPCODE_SHL,                 1, 2 },
+   [TGSI_OPCODE_AND]          = { GEN6_OPCODE_AND,                 1, 2 },
+   [TGSI_OPCODE_OR]           = { GEN6_OPCODE_OR,                  1, 2 },
    [TGSI_OPCODE_MOD]          = { TOY_OPCODE_INT_DIV_REMAINDER,   1, 2 },
-   [TGSI_OPCODE_XOR]          = { BRW_OPCODE_XOR,                 1, 2 },
+   [TGSI_OPCODE_XOR]          = { GEN6_OPCODE_XOR,                 1, 2 },
    [TGSI_OPCODE_EMIT]         = { TOY_OPCODE_EMIT,                0, 0 },
    [TGSI_OPCODE_ENDPRIM]      = { TOY_OPCODE_ENDPRIM,             0, 0 },
-   [TGSI_OPCODE_NOP]          = { BRW_OPCODE_NOP,                 0, 0 },
+   [TGSI_OPCODE_NOP]          = { GEN6_OPCODE_NOP,                 0, 0 },
    [TGSI_OPCODE_KILL_IF]      = { TOY_OPCODE_KIL,                 0, 1 },
-   [TGSI_OPCODE_END]          = { BRW_OPCODE_NOP,                 0, 0 },
-   [TGSI_OPCODE_F2I]          = { BRW_OPCODE_MOV,                 1, 1 },
+   [TGSI_OPCODE_END]          = { GEN6_OPCODE_NOP,                 0, 0 },
+   [TGSI_OPCODE_F2I]          = { GEN6_OPCODE_MOV,                 1, 1 },
    [TGSI_OPCODE_IDIV]         = { TOY_OPCODE_INT_DIV_QUOTIENT,    1, 2 },
-   [TGSI_OPCODE_IMAX]         = { BRW_OPCODE_SEL,                 1, 2 },
-   [TGSI_OPCODE_IMIN]         = { BRW_OPCODE_SEL,                 1, 2 },
-   [TGSI_OPCODE_INEG]         = { BRW_OPCODE_MOV,                 1, 1 },
-   [TGSI_OPCODE_ISHR]         = { BRW_OPCODE_ASR,                 1, 2 },
-   [TGSI_OPCODE_F2U]          = { BRW_OPCODE_MOV,                 1, 1 },
-   [TGSI_OPCODE_U2F]          = { BRW_OPCODE_MOV,                 1, 1 },
-   [TGSI_OPCODE_UADD]         = { BRW_OPCODE_ADD,                 1, 2 },
+   [TGSI_OPCODE_IMAX]         = { GEN6_OPCODE_SEL,                 1, 2 },
+   [TGSI_OPCODE_IMIN]         = { GEN6_OPCODE_SEL,                 1, 2 },
+   [TGSI_OPCODE_INEG]         = { GEN6_OPCODE_MOV,                 1, 1 },
+   [TGSI_OPCODE_ISHR]         = { GEN6_OPCODE_ASR,                 1, 2 },
+   [TGSI_OPCODE_F2U]          = { GEN6_OPCODE_MOV,                 1, 1 },
+   [TGSI_OPCODE_U2F]          = { GEN6_OPCODE_MOV,                 1, 1 },
+   [TGSI_OPCODE_UADD]         = { GEN6_OPCODE_ADD,                 1, 2 },
    [TGSI_OPCODE_UDIV]         = { TOY_OPCODE_INT_DIV_QUOTIENT,    1, 2 },
    /* a later pass will move src[2] to accumulator */
-   [TGSI_OPCODE_UMAD]         = { BRW_OPCODE_MAC,                 1, 3 },
-   [TGSI_OPCODE_UMAX]         = { BRW_OPCODE_SEL,                 1, 2 },
-   [TGSI_OPCODE_UMIN]         = { BRW_OPCODE_SEL,                 1, 2 },
+   [TGSI_OPCODE_UMAD]         = { GEN6_OPCODE_MAC,                 1, 3 },
+   [TGSI_OPCODE_UMAX]         = { GEN6_OPCODE_SEL,                 1, 2 },
+   [TGSI_OPCODE_UMIN]         = { GEN6_OPCODE_SEL,                 1, 2 },
    [TGSI_OPCODE_UMOD]         = { TOY_OPCODE_INT_DIV_REMAINDER,   1, 2 },
-   [TGSI_OPCODE_UMUL]         = { BRW_OPCODE_MUL,                 1, 2 },
-   [TGSI_OPCODE_USHR]         = { BRW_OPCODE_SHR,                 1, 2 },
-   [TGSI_OPCODE_UARL]         = { BRW_OPCODE_MOV,                 1, 1 },
-   [TGSI_OPCODE_IABS]         = { BRW_OPCODE_MOV,                 1, 1 },
+   [TGSI_OPCODE_UMUL]         = { GEN6_OPCODE_MUL,                 1, 2 },
+   [TGSI_OPCODE_USHR]         = { GEN6_OPCODE_SHR,                 1, 2 },
+   [TGSI_OPCODE_UARL]         = { GEN6_OPCODE_MOV,                 1, 1 },
+   [TGSI_OPCODE_IABS]         = { GEN6_OPCODE_MOV,                 1, 1 },
 };
 
 static void
@@ -111,7 +111,7 @@ aos_simple(struct toy_compiler *tc,
 {
    struct toy_inst *inst;
    int opcode;
-   int cond_modifier = BRW_CONDITIONAL_NONE;
+   int cond_modifier = GEN6_COND_NORMAL;
    int num_dst = tgsi_inst->Instruction.NumDstRegs;
    int num_src = tgsi_inst->Instruction.NumSrcRegs;
    int i;
@@ -125,7 +125,7 @@ aos_simple(struct toy_compiler *tc,
    }
 
    /* no need to emit nop */
-   if (opcode == BRW_OPCODE_NOP)
+   if (opcode == GEN6_OPCODE_NOP)
       return;
 
    inst = tc_add(tc);
@@ -138,12 +138,12 @@ aos_simple(struct toy_compiler *tc,
    case TGSI_OPCODE_MIN:
    case TGSI_OPCODE_IMIN:
    case TGSI_OPCODE_UMIN:
-      cond_modifier = BRW_CONDITIONAL_L;
+      cond_modifier = GEN6_COND_L;
       break;
    case TGSI_OPCODE_MAX:
    case TGSI_OPCODE_IMAX:
    case TGSI_OPCODE_UMAX:
-      cond_modifier = BRW_CONDITIONAL_GE;
+      cond_modifier = GEN6_COND_GE;
       break;
    case TGSI_OPCODE_SUB:
       src[1] = tsrc_negate(src[1]);
@@ -153,14 +153,14 @@ aos_simple(struct toy_compiler *tc,
       src[0] = tsrc_absolute(src[0]);
       break;
    case TGSI_OPCODE_IF:
-      cond_modifier = BRW_CONDITIONAL_NEQ;
+      cond_modifier = GEN6_COND_NZ;
       num_src = 2;
       assert(src[0].type == TOY_TYPE_F);
       src[0] = tsrc_swizzle1(src[0], TOY_SWIZZLE_X);
       src[1] = tsrc_imm_f(0.0f);
       break;
    case TGSI_OPCODE_UIF:
-      cond_modifier = BRW_CONDITIONAL_NEQ;
+      cond_modifier = GEN6_COND_NZ;
       num_src = 2;
       assert(src[0].type == TOY_TYPE_UD);
       src[0] = tsrc_swizzle1(src[0], TOY_SWIZZLE_X);
@@ -210,29 +210,29 @@ aos_set_on_cond(struct toy_compiler *tc,
    case TGSI_OPCODE_ISLT:
    case TGSI_OPCODE_USLT:
    case TGSI_OPCODE_FSLT:
-      cond = BRW_CONDITIONAL_L;
+      cond = GEN6_COND_L;
       break;
    case TGSI_OPCODE_SGE:
    case TGSI_OPCODE_ISGE:
    case TGSI_OPCODE_USGE:
    case TGSI_OPCODE_FSGE:
-      cond = BRW_CONDITIONAL_GE;
+      cond = GEN6_COND_GE;
       break;
    case TGSI_OPCODE_SEQ:
    case TGSI_OPCODE_USEQ:
    case TGSI_OPCODE_FSEQ:
-      cond = BRW_CONDITIONAL_EQ;
+      cond = GEN6_COND_Z;
       break;
    case TGSI_OPCODE_SGT:
-      cond = BRW_CONDITIONAL_G;
+      cond = GEN6_COND_G;
       break;
    case TGSI_OPCODE_SLE:
-      cond = BRW_CONDITIONAL_LE;
+      cond = GEN6_COND_LE;
       break;
    case TGSI_OPCODE_SNE:
    case TGSI_OPCODE_USNE:
    case TGSI_OPCODE_FSNE:
-      cond = BRW_CONDITIONAL_NEQ;
+      cond = GEN6_COND_NZ;
       break;
    default:
       assert(!"invalid aos_set_on_cond() call");
@@ -259,7 +259,7 @@ aos_set_on_cond(struct toy_compiler *tc,
    tc_MOV(tc, dst[0], zero);
    tc_CMP(tc, tdst_null(), src[0], src[1], cond);
    inst = tc_MOV(tc, dst[0], one);
-   inst->pred_ctrl = BRW_PREDICATE_NORMAL;
+   inst->pred_ctrl = GEN6_PREDCTRL_NORMAL;
 }
 
 static void
@@ -283,9 +283,9 @@ aos_compare(struct toy_compiler *tc,
       return;
    }
 
-   tc_CMP(tc, tdst_null(), src[0], zero, BRW_CONDITIONAL_L);
-   inst = tc_SEL(tc, dst[0], src[1], src[2], BRW_CONDITIONAL_NONE);
-   inst->pred_ctrl = BRW_PREDICATE_NORMAL;
+   tc_CMP(tc, tdst_null(), src[0], zero, GEN6_COND_L);
+   inst = tc_SEL(tc, dst[0], src[1], src[2], GEN6_COND_NORMAL);
+   inst->pred_ctrl = GEN6_PREDCTRL_NORMAL;
 }
 
 static void
@@ -315,13 +315,13 @@ aos_set_sign(struct toy_compiler *tc,
 
    tc_MOV(tc, dst[0], zero);
 
-   tc_CMP(tc, tdst_null(), src[0], zero, BRW_CONDITIONAL_G);
+   tc_CMP(tc, tdst_null(), src[0], zero, GEN6_COND_G);
    inst = tc_MOV(tc, dst[0], one);
-   inst->pred_ctrl = BRW_PREDICATE_NORMAL;
+   inst->pred_ctrl = GEN6_PREDCTRL_NORMAL;
 
-   tc_CMP(tc, tdst_null(), src[0], zero, BRW_CONDITIONAL_L);
+   tc_CMP(tc, tdst_null(), src[0], zero, GEN6_COND_L);
    inst = tc_MOV(tc, dst[0], neg_one);
-   inst->pred_ctrl = BRW_PREDICATE_NORMAL;
+   inst->pred_ctrl = GEN6_PREDCTRL_NORMAL;
 }
 
 static void
@@ -475,19 +475,19 @@ aos_LIT(struct toy_compiler *tc,
    tc_CMP(tc, tdst_null(),
          tsrc_swizzle1(src[0], TOY_SWIZZLE_X),
          tsrc_imm_f(0.0f),
-         BRW_CONDITIONAL_G);
+         GEN6_COND_G);
 
    inst = tc_MOV(tc,
          tdst_writemask(dst[0], TOY_WRITEMASK_Y),
          tsrc_swizzle1(src[0], TOY_SWIZZLE_X));
-   inst->pred_ctrl = BRW_PREDICATE_NORMAL;
+   inst->pred_ctrl = GEN6_PREDCTRL_NORMAL;
 
    /* clamp W to (-128, 128)? */
    inst = tc_POW(tc,
          tdst_writemask(dst[0], TOY_WRITEMASK_Z),
          tsrc_swizzle1(src[0], TOY_SWIZZLE_Y),
          tsrc_swizzle1(src[0], TOY_SWIZZLE_W));
-   inst->pred_ctrl = BRW_PREDICATE_NORMAL;
+   inst->pred_ctrl = GEN6_PREDCTRL_NORMAL;
 }
 
 static void
@@ -578,9 +578,9 @@ aos_CND(struct toy_compiler *tc,
 
    assert(!"CND untested");
 
-   tc_CMP(tc, tdst_null(), src[2], tsrc_imm_f(0.5f), BRW_CONDITIONAL_G);
-   inst = tc_SEL(tc, dst[0], src[0], src[1], BRW_CONDITIONAL_NONE);
-   inst->pred_ctrl = BRW_PREDICATE_NORMAL;
+   tc_CMP(tc, tdst_null(), src[2], tsrc_imm_f(0.5f), GEN6_COND_G);
+   inst = tc_SEL(tc, dst[0], src[0], src[1], GEN6_COND_NORMAL);
+   inst->pred_ctrl = GEN6_PREDCTRL_NORMAL;
 }
 
 static void
@@ -605,8 +605,8 @@ aos_CLAMP(struct toy_compiler *tc,
 {
    assert(!"CLAMP untested");
 
-   tc_SEL(tc, dst[0], src[0], src[1], BRW_CONDITIONAL_GE);
-   tc_SEL(tc, dst[0], src[2], tsrc_from(dst[0]), BRW_CONDITIONAL_L);
+   tc_SEL(tc, dst[0], src[0], src[1], GEN6_COND_GE);
+   tc_SEL(tc, dst[0], src[2], tsrc_from(dst[0]), GEN6_COND_L);
 }
 
 static void
@@ -742,7 +742,7 @@ aos_BRK(struct toy_compiler *tc,
         struct toy_dst *dst,
         struct toy_src *src)
 {
-   tc_add0(tc, BRW_OPCODE_BREAK);
+   tc_add0(tc, GEN6_OPCODE_BREAK);
 }
 
 static void
@@ -777,7 +777,7 @@ aos_CONT(struct toy_compiler *tc,
          struct toy_dst *dst,
          struct toy_src *src)
 {
-   tc_add0(tc, BRW_OPCODE_CONTINUE);
+   tc_add0(tc, GEN6_OPCODE_CONT);
 }
 
 static void
@@ -799,7 +799,7 @@ aos_ENDLOOP(struct toy_compiler *tc,
             struct toy_dst *dst,
             struct toy_src *src)
 {
-   tc_add0(tc, BRW_OPCODE_WHILE);
+   tc_add0(tc, GEN6_OPCODE_WHILE);
 }
 
 static void
@@ -1177,9 +1177,9 @@ soa_if(struct toy_compiler *tc,
    tsrc_transpose(src_[0], src0);
 
    if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_IF)
-      tc_IF(tc, tdst_null(), src0[0], tsrc_imm_f(0.0f), BRW_CONDITIONAL_NEQ);
+      tc_IF(tc, tdst_null(), src0[0], tsrc_imm_f(0.0f), GEN6_COND_NZ);
    else
-      tc_IF(tc, tdst_null(), src0[0], tsrc_imm_d(0), BRW_CONDITIONAL_NEQ);
+      tc_IF(tc, tdst_null(), src0[0], tsrc_imm_d(0), GEN6_COND_NZ);
 }
 
 static void
@@ -1204,11 +1204,11 @@ soa_LIT(struct toy_compiler *tc,
     * POW is calculated first because math with pred_ctrl is broken here.
     * But, why?
     */
-   tc_CMP(tc, tdst_null(), src0[0], tsrc_imm_f(0.0f), BRW_CONDITIONAL_L);
+   tc_CMP(tc, tdst_null(), src0[0], tsrc_imm_f(0.0f), GEN6_COND_L);
    inst = tc_MOV(tc, dst0[1], tsrc_imm_f(0.0f));
-   inst->pred_ctrl = BRW_PREDICATE_NORMAL;
+   inst->pred_ctrl = GEN6_PREDCTRL_NORMAL;
    inst = tc_MOV(tc, dst0[2], tsrc_imm_f(0.0f));
-   inst->pred_ctrl = BRW_PREDICATE_NORMAL;
+   inst->pred_ctrl = GEN6_PREDCTRL_NORMAL;
 }
 
 static void