diff options
| author | Ilia Mirkin <imirkin@alum.mit.edu> | 2014-04-25 22:40:42 -0400 |
|---|---|---|
| committer | Ilia Mirkin <imirkin@alum.mit.edu> | 2014-04-28 19:05:16 -0400 |
| commit | b4b20d42f6a8cd5aec3ba529a0b8d6ea22e73305 (patch) | |
| tree | 6e4561bca3585baa22a3de0cd87b849f78f3d523 /src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp | |
| parent | 1db993f2fe1c2b43a9658efba6eac93665bb859c (diff) | |
| download | external_mesa3d-b4b20d42f6a8cd5aec3ba529a0b8d6ea22e73305.zip external_mesa3d-b4b20d42f6a8cd5aec3ba529a0b8d6ea22e73305.tar.gz external_mesa3d-b4b20d42f6a8cd5aec3ba529a0b8d6ea22e73305.tar.bz2 | |
nvc0/ir: add support for new bitfield manipulation opcodes
This adds support for:
IBFE, UBFE, BFI, LSB, IMSB, UMSB, BREV, POPC
Which are all required for ARB_gs5 support.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Diffstat (limited to 'src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp')
| -rw-r--r-- | src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp index c747f3e..395d5b5 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp @@ -124,7 +124,10 @@ static const struct opProperties _initProps[] = { OP_DFDX, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0 }, { OP_DFDY, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0 }, { OP_CALL, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0 }, - { OP_INSBF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4 }, + { OP_POPCNT, 0x0, 0x0, 0x3, 0x0, 0x2, 0x2 }, + { OP_INSBF, 0x0, 0x0, 0x0, 0x0, 0x6, 0x2 }, + { OP_EXTBF, 0x0, 0x0, 0x0, 0x0, 0x2, 0x2 }, + { OP_BFIND, 0x0, 0x0, 0x1, 0x0, 0x1, 0x1 }, { OP_PERMT, 0x0, 0x0, 0x0, 0x0, 0x6, 0x2 }, { OP_SET_AND, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 }, { OP_SET_OR, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 }, @@ -393,6 +396,8 @@ TargetNVC0::isModSupported(const Instruction *insn, int s, Modifier mod) const case OP_AND: case OP_OR: case OP_XOR: + case OP_POPCNT: + case OP_BFIND: break; case OP_SET: if (insn->sType != TYPE_F32) |