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author | Ilia Mirkin <imirkin@alum.mit.edu> | 2015-10-29 22:18:25 -0400 |
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committer | Ilia Mirkin <imirkin@alum.mit.edu> | 2015-10-29 22:42:38 -0400 |
commit | f768eaa87d3413610df645dcc94b06fa1fbe0005 (patch) | |
tree | c63fd8c092f06ad1e35ac7ddf0a1a29ee2c2a4a6 /src/gallium/drivers/nouveau/nv50/nv50_shader_state.c | |
parent | 85ee2f7fcf59991308632d7e3a64e9a1d22fe24c (diff) | |
download | external_mesa3d-f768eaa87d3413610df645dcc94b06fa1fbe0005.zip external_mesa3d-f768eaa87d3413610df645dcc94b06fa1fbe0005.tar.gz external_mesa3d-f768eaa87d3413610df645dcc94b06fa1fbe0005.tar.bz2 |
nv50: allow per-sample interpolation to be forced via rast
Uses the same technique as for nvc0 of fixups before upload, and
evicting in case of state change. Removes one source of variants kept by
st/mesa.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Diffstat (limited to 'src/gallium/drivers/nouveau/nv50/nv50_shader_state.c')
-rw-r--r-- | src/gallium/drivers/nouveau/nv50/nv50_shader_state.c | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_shader_state.c b/src/gallium/drivers/nouveau/nv50/nv50_shader_state.c index 941555f..b3fece0 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_shader_state.c +++ b/src/gallium/drivers/nouveau/nv50/nv50_shader_state.c @@ -168,11 +168,23 @@ nv50_fragprog_validate(struct nv50_context *nv50) { struct nouveau_pushbuf *push = nv50->base.pushbuf; struct nv50_program *fp = nv50->fragprog; + struct pipe_rasterizer_state *rast = &nv50->rast->pipe; - fp->fp.sample_interp = nv50->min_samples > 1; + if (fp->fp.force_persample_interp != rast->force_persample_interp) { + /* Force the program to be reuploaded, which will trigger interp fixups + * to get applied + */ + if (fp->mem) + nouveau_heap_free(&fp->mem); + + fp->fp.force_persample_interp = rast->force_persample_interp; + } + + if (fp->mem && !(nv50->dirty & (NV50_NEW_FRAGPROG | NV50_NEW_MIN_SAMPLES))) + return; if (!nv50_program_validate(nv50, fp)) - return; + return; nv50_program_update_context_state(nv50, fp, 1); BEGIN_NV04(push, NV50_3D(FP_REG_ALLOC_TEMP), 1); |