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authorMarek Olšák <marek.olsak@amd.com>2016-06-08 21:00:22 +0200
committerMarek Olšák <marek.olsak@amd.com>2016-06-14 20:22:16 +0200
commit4eea710b0d050275b532dbc117da97f569e5fb1e (patch)
treeaf75ecd64d16f85497d637bc825f22569040f129 /src/gallium/drivers/radeon/r600_pipe_common.h
parent373060652c889bb85d5a4673405d77ee75fb6fdc (diff)
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radeonsi: try to hit direct hw MSAA resolve by changing micro mode in clear
We could also do MSAA resolve in a compute shader like Vulkan and remove these workarounds. v2: comment the magic numbers Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Diffstat (limited to 'src/gallium/drivers/radeon/r600_pipe_common.h')
-rw-r--r--src/gallium/drivers/radeon/r600_pipe_common.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
index edfae95..57fa9e3 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -252,6 +252,7 @@ struct r600_texture {
uint64_t dcc_offset; /* 0 = disabled */
unsigned cb_color_info; /* fast clear enable bit */
unsigned color_clear_value[2];
+ unsigned last_msaa_resolve_target_micro_mode;
/* Depth buffer compression and fast clear. */
struct r600_htile_info htile;