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| author | Marek Olšák <marek.olsak@amd.com> | 2014-12-29 14:45:49 +0100 |
|---|---|---|
| committer | Marek Olšák <marek.olsak@amd.com> | 2015-01-07 12:06:43 +0100 |
| commit | edf18da85dd3b1865c4faaba650a8fa371b7103c (patch) | |
| tree | 5cf04bf87559911e77dd5c57093bb2d64503e390 /src/gallium/drivers/radeon/radeon_video.c | |
| parent | 73c2b0d18c51459697d8ec194ecfc4438c98c139 (diff) | |
| download | external_mesa3d-edf18da85dd3b1865c4faaba650a8fa371b7103c.zip external_mesa3d-edf18da85dd3b1865c4faaba650a8fa371b7103c.tar.gz external_mesa3d-edf18da85dd3b1865c4faaba650a8fa371b7103c.tar.bz2 | |
radeonsi: only flush the right set of caches for CP DMA operations
That's either framebuffer caches or caches for shader resources.
The motivation is that framebuffer caches need to be flushed very rarely
here.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Diffstat (limited to 'src/gallium/drivers/radeon/radeon_video.c')
| -rw-r--r-- | src/gallium/drivers/radeon/radeon_video.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeon/radeon_video.c b/src/gallium/drivers/radeon/radeon_video.c index f6cfdff..1420798 100644 --- a/src/gallium/drivers/radeon/radeon_video.c +++ b/src/gallium/drivers/radeon/radeon_video.c @@ -122,7 +122,8 @@ void rvid_clear_buffer(struct pipe_context *context, struct rvid_buffer* buffer) { struct r600_common_context *rctx = (struct r600_common_context*)context; - rctx->clear_buffer(context, &buffer->res->b.b, 0, buffer->res->buf->size, 0); + rctx->clear_buffer(context, &buffer->res->b.b, 0, buffer->res->buf->size, + 0, false); context->flush(context, NULL, 0); } |