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| author | Marek Olšák <marek.olsak@amd.com> | 2016-10-10 18:51:24 +0200 |
|---|---|---|
| committer | Marek Olšák <marek.olsak@amd.com> | 2016-10-12 18:29:40 +0200 |
| commit | 40e1f7e09bf1bc9b8ed6f847562bbb7154025420 (patch) | |
| tree | 914d8dab62758e5488cda94e215804aee916cc23 /src/gallium/drivers/radeonsi/si_compute.c | |
| parent | 8cdce30cc20983dcb971dd906a9a9007e282081d (diff) | |
| download | external_mesa3d-40e1f7e09bf1bc9b8ed6f847562bbb7154025420.zip external_mesa3d-40e1f7e09bf1bc9b8ed6f847562bbb7154025420.tar.gz external_mesa3d-40e1f7e09bf1bc9b8ed6f847562bbb7154025420.tar.bz2 | |
radeonsi: use TC write-back instead of full cache invalidation
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_compute.c')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_compute.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c index 632839f..e785106 100644 --- a/src/gallium/drivers/radeonsi/si_compute.c +++ b/src/gallium/drivers/radeonsi/si_compute.c @@ -701,7 +701,7 @@ static void si_launch_grid( /* The hw doesn't read the indirect buffer via TC L2. */ if (r600_resource(info->indirect)->TC_L2_dirty) { - sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2; + sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2; r600_resource(info->indirect)->TC_L2_dirty = false; } } |