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| author | Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> | 2016-03-27 11:14:34 +0200 |
|---|---|---|
| committer | Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> | 2016-04-19 18:10:31 +0200 |
| commit | 7a92c0842892bf55a82b7d95ab5a3b7dfbb83407 (patch) | |
| tree | 67bea5002d5768b610169a98f6e69e59f502dac3 /src/gallium/drivers/radeonsi/si_descriptors.c | |
| parent | e764ee13ae21e3c1dbda24daeb2d08c5e7c81871 (diff) | |
| download | external_mesa3d-7a92c0842892bf55a82b7d95ab5a3b7dfbb83407.zip external_mesa3d-7a92c0842892bf55a82b7d95ab5a3b7dfbb83407.tar.gz external_mesa3d-7a92c0842892bf55a82b7d95ab5a3b7dfbb83407.tar.bz2 | |
radeonsi: do not do two full flushes on every compute dispatch
v2: Add more CS_PARTIAL_FLUSH events.
Essentially every place with waits on finishing for pixel shaders
also has a write after read hazard with compute shaders.
Invalidating L2 waits implicitly on pixel and compute shaders,
so, we don't need a CS_PARTIAL_FLUSH for switching FBO.
v3: Add CS_PARTIAL_FLUSH events even if we already have INV_GLOBAL_L2.
According to Marek the INV_GLOBAL_L2 events don't wait for compute
shaders to finish, so wait for them explicitly.
Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_descriptors.c')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_descriptors.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index 301a865..1580e61 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -1032,7 +1032,8 @@ static void si_set_streamout_targets(struct pipe_context *ctx, * start writing to the targets. */ if (num_targets) - sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH; + sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH | + SI_CONTEXT_CS_PARTIAL_FLUSH; /* Streamout buffers must be bound in 2 places: * 1) in VGT by setting the VGT_STRMOUT registers |