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| author | Marek Olšák <marek.olsak@amd.com> | 2016-10-02 15:45:15 +0200 |
|---|---|---|
| committer | Marek Olšák <marek.olsak@amd.com> | 2016-10-04 16:11:58 +0200 |
| commit | e43bd861e8182bd93c54631185e6018fc243aea3 (patch) | |
| tree | 99e90d756219450ac8fba93c87b7ff4e65accad4 /src/gallium/drivers/radeonsi/si_descriptors.c | |
| parent | b523a9ddc5447ce03c686154ebbc5b1229e5d0a4 (diff) | |
| download | external_mesa3d-e43bd861e8182bd93c54631185e6018fc243aea3.zip external_mesa3d-e43bd861e8182bd93c54631185e6018fc243aea3.tar.gz external_mesa3d-e43bd861e8182bd93c54631185e6018fc243aea3.tar.bz2 | |
radeonsi: track buffer bind history
similar to gl_buffer_object::UsageHistory
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_descriptors.c')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_descriptors.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index 3066323..066faa1 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -414,7 +414,9 @@ static void si_set_sampler_view(struct si_context *sctx, pipe_sampler_view_reference(&views->views[slot], view); memcpy(desc, rview->state, 8*4); - if (rtex->resource.b.b.target != PIPE_BUFFER) { + if (rtex->resource.b.b.target == PIPE_BUFFER) { + rtex->resource.bind_history |= PIPE_BIND_SAMPLER_VIEW; + } else { bool is_separate_stencil = rtex->db_compatible && rview->is_stencil_sampler; @@ -640,6 +642,7 @@ static void si_set_shader_image(struct si_context *ctx, view->u.buf.size, descs->list + slot * 8); images->compressed_colortex_mask &= ~(1 << slot); + res->bind_history |= PIPE_BIND_SHADER_IMAGE; } else { static const unsigned char swizzle[4] = { 0, 1, 2, 3 }; struct r600_texture *tex = (struct r600_texture *)res; @@ -1032,6 +1035,8 @@ static void si_set_constant_buffer(struct si_context *sctx, } else { pipe_resource_reference(&buffer, input->buffer); va = r600_resource(buffer)->gpu_address + input->buffer_offset; + /* Only track usage for non-user buffers. */ + r600_resource(buffer)->bind_history |= PIPE_BIND_CONSTANT_BUFFER; } /* Set the descriptor. */ @@ -1157,6 +1162,8 @@ static void si_set_shader_buffers(struct pipe_context *ctx, radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx, buf, buffers->shader_usage, buffers->priority, true); + buf->bind_history |= PIPE_BIND_SHADER_BUFFER; + buffers->enabled_mask |= 1u << slot; descs->dirty_mask |= 1u << slot; sctx->descriptors_dirty |= @@ -1363,6 +1370,8 @@ static void si_set_streamout_targets(struct pipe_context *ctx, buffers->shader_usage, RADEON_PRIO_SHADER_RW_BUFFER, true); + r600_resource(buffer)->bind_history |= PIPE_BIND_STREAM_OUTPUT; + buffers->enabled_mask |= 1u << bufidx; } else { /* Clear the descriptor and unset the resource. */ |