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author | Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> | 2016-04-13 22:31:17 +0200 |
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committer | Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> | 2016-04-19 18:10:30 +0200 |
commit | 8fee75d606e83b1f0d665fef9ea59ba24fc6682d (patch) | |
tree | 91581e6f81f8d4b4824e2a4aff01f05854228420 /src/gallium/drivers/radeonsi/si_hw_context.c | |
parent | 7201230582e060aa2eb79c825d3188b437ef7bb8 (diff) | |
download | external_mesa3d-8fee75d606e83b1f0d665fef9ea59ba24fc6682d.zip external_mesa3d-8fee75d606e83b1f0d665fef9ea59ba24fc6682d.tar.gz external_mesa3d-8fee75d606e83b1f0d665fef9ea59ba24fc6682d.tar.bz2 |
radeonsi: Create CE IB.
Based on work by Marek Olšák.
v2: Add preamble IB.
Leaves the load packet in the space calculation as the
radeon winsys might not be able to support a premable.
The added space calculation may look expensive, but
is converted to a constant with (at least) -O2 and -O3.
v3: - Fix code style.
- Remove needed space for vertex buffer descriptors.
- Fail when the preamble cannot be created.
Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_hw_context.c')
-rw-r--r-- | src/gallium/drivers/radeonsi/si_hw_context.c | 35 |
1 files changed, 34 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c b/src/gallium/drivers/radeonsi/si_hw_context.c index b621b55..5294898 100644 --- a/src/gallium/drivers/radeonsi/si_hw_context.c +++ b/src/gallium/drivers/radeonsi/si_hw_context.c @@ -26,10 +26,41 @@ #include "si_pipe.h" +static unsigned si_descriptor_list_cs_space(unsigned count, unsigned element_size) +{ + /* Ensure we have enough space to start a new range in a hole */ + assert(element_size >= 3); + + /* 5 dwords for possible load to reinitialize when we have no preamble + * IB + 5 dwords for write to L2 + 3 bytes for every range written to + * CE RAM. + */ + return 5 + 5 + 3 + count * element_size; +} + +static unsigned si_ce_needed_cs_space(void) +{ + unsigned space = 0; + + space += si_descriptor_list_cs_space(SI_NUM_CONST_BUFFERS, 4); + space += si_descriptor_list_cs_space(SI_NUM_RW_BUFFERS, 4); + space += si_descriptor_list_cs_space(SI_NUM_SHADER_BUFFERS, 4); + space += si_descriptor_list_cs_space(SI_NUM_SAMPLERS, 16); + space += si_descriptor_list_cs_space(SI_NUM_IMAGES, 8); + + space *= SI_NUM_SHADERS; + + /* Increment CE counter packet */ + space += 2; + + return space; +} + /* initialize */ void si_need_cs_space(struct si_context *ctx) { struct radeon_winsys_cs *cs = ctx->b.gfx.cs; + struct radeon_winsys_cs *ce_ib = ctx->ce_ib; struct radeon_winsys_cs *dma = ctx->b.dma.cs; /* Flush the DMA IB if it's not empty. */ @@ -53,7 +84,9 @@ void si_need_cs_space(struct si_context *ctx) /* If the CS is sufficiently large, don't count the space needed * and just flush if there is not enough space left. */ - if (unlikely(cs->cdw > cs->max_dw - 2048)) + if (unlikely(cs->cdw > cs->max_dw - 2048 || + (ce_ib && ce_ib->max_dw - ce_ib->cdw < + si_ce_needed_cs_space()))) ctx->b.gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL); } |